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AD15–AD8
AO15–AO8
ALE
ARDY
3-2
Address and Data Bus, Am186EM Microcontroller Only
(input/output, three-state, synchronous, level-sensitive)
AD15–AD8—These time-multiplexed pins supply partial memory or
I/O addresses, as well as data, to the system. This bus supplies an
address to the system during the first period of a bus cycle (t
supplies data to the system during the remaining periods of that cycle
(t
, t
, and t
).
2
3
4
The address phase of these pins can be disabled. See the ADEN
description with the BHE/ADEN pin. When WHB is not asserted, these
pins are three-stated during t
During a bus hold or reset condition, the address and data bus is in a
high-impedance state. During a power-on reset, the address and data
bus pins (AD15–AD0 for the Am186EM, AO15–AO8 and AD7–AD0 for
the Am188EM) can also be used to load system configuration
information into the internal Reset Configuration register.
Address-Only Bus, Am188EM Microcontroller Only
(output, three-state, synchronous, level-sensitive)
AO15–AO8—The address-only bus (AO15–AO8) contains valid high-
order address bits from bus cycles t
during a bus hold or reset.
On the Am188EM microcontroller, AO15–AO8 combine with AD7–AD0
to form a complete multiplexed address bus while AD7–AD0 is the 8-bit
data bus.
The address phase of these pins can be disabled during t
ADEN description with the BHE/ADEN pin.
During a power-on reset on the Am188EM microcontroller, the AO15–
AO8 and AD7–AD0 pins can also be used to load system configuration
information into an internal register for later use.
Address Latch Enable (output, synchronous)
ALE—This pin indicates to the system that an address appears on the
address and data bus (AD15–AD0 for the Am186EM or AO15–AO8
and AD7–AD0 for the Am188EM). The address is guaranteed valid on
the trailing edge of ALE.
Asynchronous Ready (input, asynchronous, level-sensitive)
This pin indicates to the microcontroller that the addressed memory
space or I/O device will complete a data transfer. The ARDY pin accepts
a rising edge that is asynchronous to CLKOUTA and is active High. The
falling edge of ARDY must be synchronized to CLKOUTA. To always
assert the ready condition to the microcontroller, tie ARDY High. If the
system does not use ARDY, tie the pin Low to yield control to SRDY.
System Overview
, t
, and t
.
2
3
4
–t
. These outputs are floated
1
4
), and it
1
. See the
1
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