AMD AM186EM User Manual page 183

Serial Port Status Register
description 10-4
Serial Port Transmit Data Register
description 10-5
SFNM bit (Special Fully Nested Mode) 7-13
signal description
A1 (Latched Address Bit 1) 3-8
A19-A0 (Address Bus) 3-1
A2 (Latched Address Bit 2) 3-8
AD15-AD0 (Address and Data Bus) 3-2
AD7-AD0 (Address and Data Bus) 3-1
ALE (Address Latch Enable) 3-2
ARDY (Asynchronous Ready) 3-2
BHE (Bus High Enable) 3-3
CLKDIV2 (Clock Divide by 2) 3-12
CLKOUTA (Clock Output A) 3-3
CLKOUTB (Clock Output B) 3-4
DEN (Data Enable) 3-4
DRQ1-DRQ0 (DMA Requests) 3-4
DT/R (Data Transmit or Receive) 3-4
HLDA (Bus Hold Acknowledge) 3-4
HOLD (Bus Hold Request) 3-4
INT0 (Maskable Interrupt Request 0) 3-5
INT1 (Maskable Interrupt Request 1) 3-5
INT2 (Maskable Interrupt Request 2) 3-5
INT3 (Maskable Interrupt Request 3) 3-6
INT4 (Maskable Interrupt Request 4) 3-6
INTA0 (Interrupt Acknowledge 0) 3-5
INTA1 (Interrupt Acknowledge 1) 3-6
IRQ (Slave Interrupt Request) 3-6
LCS (Lower Memory Chip Select) 3-6
MA15-MA7 (Multiplexed Address Bus) 3-2
MCS2-MCS0 (Midrange Memory Chip Selects 2-0)
3-7
MCS3 (Midrange Memory Chip Select 3) 3-7
NMI (Nonmaskable Interrupt) 3-7
ONCE0 (ONCE Mode Request 0) 3-6
ONCE1 (ONCE Mode Request 1) 3-13
PCS30-PCS0 (Peripheral Chip Selects 3-0) 3-7
PCS5 (Peripheral Chip Select 5) 3-8
PCS6 (Peripheral Chip Select 6) 3-8
PIO31-PIO0 (Programmable I/O Pins 31-0) 3-8
PLLBYPS (PLL Bypass) 3-14
RD (Read Strobe) 3-11
RES (Reset) 3-11
RFSH (Automatic Refresh) 3-7
RFSH2/ADEN (Refresh 2/Address Enable) 3-11
RXD (Receive Data) 3-11
S2-S0 (Bus Cycle Status 2-0) 3-11
S6 (Bus Cycle Status 6) 3-12
SCLK (Serial Clock) 3-12
SDATA (Serial Data) 3-12
SDEN1-SDEN0 (Serial Data Enables 1-0) 3-12
SELECT (Slave Select) 3-5
SRDY (Synchronous Ready) 3-13
TMRIN0 (Timer Input 0) 3-13
TMRIN1 (Timer Input 1) 3-13
TMROUT0 (Timer Output 0) 3-13
TMROUT1 (Timer Output 1) 3-13
TXD (Transmit Data) 3-13
UCS (Upper Memory Chip Select) 3-13
UZI (Upper Zero Indicate) 3-14
WB (Write Byte) 3-14
WHB (Write High Byte) 3-14
WLB (Write Low Byte) 3-14
WR (Write Strobe) 3-14
SINC bit (Source Increment) 9-4
Slave mode interrupts 7-28
Slave mode nesting 7-28
SM/IO bit (Source Address Space Select) 9-3
Software interrupt 7-3
Special fully nested mode 7-11
Specific EndofInterrupt Register
description
Slave mode 7-35
SPI bit (Serial Port Interrupt InService) 7-22
SPI bit (Serial Port Interrupt Mask) 7-24
SPI bit (Serial Port Interrupt Request) 7-21
SR field (Receive Data) 11-6
SRDY signal (Synchronous Ready)
definition 3-13
ST bit (Start/Stop DMA Channel) 9-4
STP bit (Stop Bits) 10-3
SYN1-SYN0 field (Synchronization Type) 9-4
Synchronous Serial Control Register
description 11-4
Synchronous Serial Receive Register
description 11-6
Synchronous Serial Status Register
description 11-3
Synchronous Serial Transmit 0 Register
description 11-5
Index
I-9