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Slave mode 7-33
PRM2-PRM0 field (Priority Field Mask) 7-23, 7-33
Processor Release Level Register
description 4-6
product support
bulletin board service iii
documentation and literature iii
technical support hotline iii
PSE bit (PSRAM Mode Enable) 5-7
R
R19-R8 field (Relocation Address Bits) 4-4
R1-R0 field (Wait State Value)
Low Memory Chip Select Register 5-7
Midrange Memory Chip Select Register 5-9
PCS and MCS Auxiliary Register 5-11
Upper Memory Chip Select Register 5-5
R2 bit (Ready Mode)
Low Memory Chip Select Register 5-7
Midrange Memory Chip Select Register 5-9
PCS and MCS Auxiliary Register 5-11
Upper Memory Chip Select Register 5-5
R7 field (Address Disable)
Upper Memory Chip Select Register 5-5, 5-7
RC field (Reset Configuration) 4-5
RC8-RC0 field (Refresh Counter Reload Value) 6-2
RD signal (Read Strobe)
definition 3-11
RDATA field (Receive Data) 10-6
RDR bit (Receive Data Ready) 10-4
RE/TE bit (Receive/Transmit Error Detect) 11-3
registers
Clock Prescaler (CDRAM, Offset E2h) 6-2
DMA 0 Control (D0CON, Offset CAh) 9-3
DMA 0 Interrupt Control (DMA0CON, Offset 34h) 7-
17, 7-29
DMA 0 Source Address High (D0SRCH, Offset
C2h) 9-8
DMA 0 Source Address Low (D0SRCL, Offset C0h)
9-9
DMA 0 Transfer Count (D0TC, Offset C8h) 9-5
DMA 1 Control (D1CON, Offset DAh) 9-3
DMA 1 Destination Address High (D0DSTH, Offset
C6h) 9-6
DMA 1 Destination Address High (D1DSTH, Offset
D6h) 9-6
DMA 1 Destination Address Low (D0DSTL, Offset
C4h) 9-7
DMA 1 Destination Address Low (D1DSTL, Offset
D4h) 9-7
DMA 1 Interrupt Control (DMA1CON, Offset 36h) 7-
17, 7-29
DMA 1 Source Address High (D1SRCH, Offset
D2h) 9-8
DMA 1 Source Address Low (D1SRCL, Offset D0h)
9-9
DMA 1 Transfer Count (D1TC, Offset D8h) 9-5
Enable RCU (EDRAM, Offset E4h) 6-2
EndofInterrupt (EOI, Offset 22h) 7-27
InService (INSERV, Offset 2Ch) 7-22, 7-32
INT0 Control (INT0, Offset 38h)
Master mode 7-13
INT1 Control (INT1, Offset 3Ah)
Master mode 7-13
INT2 Control (INT2, Offset 3Ch)
Master mode 7-15
INT3 Control (INT3, Offset 3Eh)
Master mode 7-15
INT4 Control (INT4, Offset 40h)
Master mode 7-16
Interrupt Mask (IMASK, Offset 28h) 7-24, 7-34
Interrupt Request (REQST, Offset 2Eh) 7-21, 7-31
Interrupt Status (INSTS, Offset 30h) 7-20
Interrupt Status (INTSTS, Offset 30h) 7-30
Interrupt Vector (INTVEC, Offset 20h) 7-36
Low Memory Chip Select (LMCS, Offset A2h) 5-6
Memory Partition (MDRAM, Offset E0h) 6-1
Midrange Memory Chip Select (MMCS, Offset A6h)
5-8
PCS and MCS Auxiliary (MPCS, Offset A8h) 5-10
Peripheral Chip Select (PACS, Offset A4h) 5-12
Peripheral Control Block Relocation (RELREG, Off-
set FEh) 4-4
PIO Data 0 (PDATA0, Offset 74h) 12-5
PIO Data 1 (PDATA1, Offset 7Ah) 12-5
PIO Direction 0 (PDIR0, Offset 72h) 12-4
PIO Direction 1 (PDIR1, Offset 78h) 12-4
PIO Mode 0 (PIOMODE0, Offset 70h) 12-3
PIO Mode 1 (PIOMODE1, Offset 76h) 12-3
Poll (POLL, Offset 24h) 7-26
Poll Status (POLLST, Offset 26h) 7-25
PowerSave Control (PDCON, Offset F0h) 4-7
Priority Mask (PRIMSK, Offset 2Ah) 7-23, 7-33
Processor Release Level (PRL, Offset F4) 4-6
Reset Configuration (RESCON, Offset F6h) 4-5
Index
I-7
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