AMD AM186EM User Manual page 178

E
E bit (Enable RCU) 6-2
EN bit (Enable Bit)
Timer 0 Mode/Control Register 8-3
Timer 1 Mode/Control Register 8-3
Timer 2 Mode/Control Register 8-5
EN bit (Enable PowerSave Mode) 4-7
Enable RCU Register
description 6-2
Endofinterrupt processing 7-11
EndofInterrupt Register
description
Master mode 7-27
EOI 7-11
EX bit (Pin Selector) 5-11
EXT bit (External Clock Bit)
Timer 0 Mode/Control Register 8-4
Timer 1 Mode/Control Register 8-4
External interrupt acknowledge bus cycles table 7-7
F
F2-F0 field (Clock Divisor Select) 4-7
FER bit (Framing Error) 10-4
Figure
external interrupt acknowledge bus cycles 7-7
Fully nested mode interrupt controller connections
7-9
Fully nested mode 7-9
Fully nested mode interrupt controller connections 7-9
H
HLDA signal (Bus Hold Acknowledge)
definition 3-4
HOLD signal (Bus Hold Request)
definition 3-4
I
I4-I0 field (Interrupt InService) 7-22
I4-I0 field (Interrupt Mask) 7-24
I4-I0 field (Interrupt Requests) 7-21
IF (the interrupt enable flag) 7-2
INH bit (Inhibit Bit)
Timer 0 Mode/Control Register 8-3
Timer 1 Mode/Control Register 8-3
I-4
Timer 2 Mode/Control Register 8-5
InService Register
description
Master mode 7-22
Slave mode 7-32
Instruction exceptions 7-3
INT bit (Interrupt Bit)
Timer 0 Mode/Control Register 8-3
Timer 1 Mode/Control Register 8-3
Timer 2 Mode/Control Register 8-5
INT0 Control Register
description
Master mode 7-13
INT0 signal (Maskable Interrupt Request 0)
definition 3-5
INT1 Control Register
description
Master mode 7-13
INT1 signal (Maskable Interrupt Request 1)
definition 3-5
INT2 Control Register
description
Master mode 7-15
INT2 signal (Maskable Interrupt Request 2)
definition 3-5
INT3 Control Register
description
Master mode 7-15
INT3 signal (Maskable Interrupt Request 3)
definition 3-6
INT4 Control Register
description
Master mode 7-16
INT4 signal (Maskable Interrupt Request 4)
definition 3-6
INTA0 signal (Interrupt Acknowledge 0)
definition 3-5
INTA1 signal (Interrupt Acknowledge 1)
definition 3-6
Interrupt acknowledge 7-7
Interrupt conditions and sequence 7-4
Interrupt control unit 7-1
Interrupt controller registers
master mode 7-12
slave mode 7-28
Interrupt controller reset conditions 7-8
Interrupt enable flag (IF) 7-2
Index