AMD AM186EM User Manual page 35

request is received. A HOLD request is second only to DRAM refresh
requests in priority of activity requests received by the processor. This
implies that if a HOLD request is received just as a DMA transfer begins,
the HOLD latency can be as great as 4 bus cycles. This occurs if a DMA
word transfer operation is taking place (Am186EM microcontroller only)
from an odd address to an odd address. This is a total of 16 clock cycles
or more if wait states are required. In addition, if locked transfers are
performed, the HOLD latency time is increased by the length of the
locked transfer.
INT0 Maskable Interrupt Request 0 (input, asynchronous)
This pin indicates to the microcontroller that an interrupt request has
occurred. If the INT0 pin is not masked, the microcontroller transfers
program execution to the location specified by the INT0 vector in the
microcontroller interrupt vector table. Interrupt requests are
synchronized internally, and can be edge-triggered or level-triggered.
To guarantee the interrupt is recognized, the device issuing the request
must continue asserting INT0 until the request is acknowledged.
INT1/SELECT Maskable Interrupt Request 1 (input, asynchronous)
Slave Select (input, asynchronous)
INT1—This pin indicates to the microcontroller that an interrupt request
has occurred. If the INT1 pin is not masked, the microcontroller transfers
program execution to the location specified by the INT1 vector in the
microcontroller interrupt vector table. Interrupt requests are synchro-
nized internally, and can be edge-triggered or level-triggered. To guar-
antee the interrupt is recognized, the device issuing the request must
continue asserting INT1 until the request is acknowledged.
SELECT—When the microcontroller interrupt control unit is operating
as a slave to an external master interrupt controller, this pin indicates
to the microcontroller that an interrupt type appears on the address and
data bus. The INT0 pin must indicate to the microcontroller that an
interrupt has occurred before the SELECT pin indicates to the
microcontroller that the interrupt type appears on the bus.
INT2/INTA0 Maskable Interrupt Request 2 (input, asynchronous)
Interrupt Acknowledge 0 (output, synchronous)
INT2—This pin indicates to the microcontroller that an interrupt request
has occurred. If the INT2 pin is not masked, the microcontroller transfers
program execution to the location specified by the INT2 vector in the
microcontroller interrupt vector table. Interrupt requests are
synchronized internally, and can be edge-triggered or level-triggered.
To guarantee the interrupt is recognized, the device issuing the request
must continue asserting INT2 until the request is acknowledged. INT2
becomes INTA0 when INT0 is configured in cascade mode.
INTA0—When the microcontroller interrupt control unit is operating in
cascade mode, this pin indicates to the system that the microcontroller
needs an interrupt type to process the interrupt request on INT0. The
peripheral issuing the interrupt request must provide the microcontroller
with the corresponding interrupt type.
System Overview
3-5