Interrupt Request Register (Reqst, Offset 2Eh); (Master Mode) - AMD AM186EM User Manual

7.3.8

Interrupt Request Register (REQST, Offset 2Eh)

(Master Mode)

The hardware interrupt sources have interrupt request bits inside the interrupt controller.
A read from this register yields the status of these bits. The Interrupt Request register is a
read-only register. The format of the REQST register is shown in Figure 7-11.
The Am186EM and Am188EM microcontrollers define three new bits to report the state of
INT4, the Watchdog Timer, and the asynchronous serial port.
For internal interrupts (SPI, WD, D1, D0, and TMR), the corresponding bit is set to 1 when
the device requests an interrupt. The bit is reset during the internally generated interrupt
acknowledge.
For INT4–INT0 external interrupts, the corresponding bit (I4–I0) reflects the current value
of the external signal. The device must hold this signal High until the interrupt is serviced.
Generally the interrupt service routine signals the external device to remove the interrupt
request.
Figure 7-11 Interrupt Request Register (REQST, offset 2Eh)
The REQST register is undefined on reset.
Bits 15–11: Reserved
Bit 10: Serial Port Interrupt Request (SPI)—This bit indicates the interrupt state of the
serial port. If enabled, the SPI bit is the logical OR of all possible serial port interrupt sources
(THRE, RDR, BRKI, FER, PER, and OER status bits).
Bit 9: Watchdog Timer Interrupt Request (WD)—When this bit is set to 1, the Watchdog
Timer has an interrupt pending.
Bits 8–4: Interrupt Requests (I4–I0)—When set to 1, the corresponding INT pin has an
interrupt pending (i.e., when INT0 is pending, I0 is set). These bits reflect the status of the
external pin.
Bits 3–2: DMA Channel Interrupt Request (D1–D0)—When set to 1, the corresponding
DMA channel has an interrupt pending.
Bit 1: Reserved
Bit 0: Timer Interrupt Request (TMR)—This bit indicates the state of the timer interrupts.
This bit is the logical OR of the timer interrupt requests. When set to a 1, this bit indicates
that the timer control unit has an interrupt pending.
The Interrupt Status register indicates the specific timer that is requesting an interrupt. See
section 7.3.7.
7
15
Reserved
SPI I4
WD I3
Interrupt Control Unit
0
I2 I0 D0 TMR
I1 D1 Res
7-21