AMD AM186EM User Manual page 179

Interrupt mask bit 7-2
Interrupt Mask Register
description
Master mode 7-24
Slave mode 7-34
Interrupt priority 7-2, 7-5
Interrupt Request Register
description
Master mode 7-21
Slave mode 7-31
Interrupt return (IRET) 7-4
Interrupt Status Register
description
Master mode 7-20
Slave mode 7-30
Interrupt type 7-1
Interrupt types 7-6
Interrupt types table 7-3
Interrupt Vector Register
description
Slave mode 7-36
Interrupt vector table 7-2
Interrupts
array BOUNDs exception 7-6
breakpoint 7-6
cascade mode 7-10
divide error exception 7-6
EOI 7-11
ESC opcode exception 7-6
fully nested mode 7-9
Instruction exceptions 7-3
INTO overflow detected 7-6
Maskable and nonmaskable 7-2
master mode operation 7-9
nonmaskable (NMI) 7-6
polled 7-11
slave mode 7-28
slave mode nesting 7-28
Special fully nested mode 7-11
trace 7-6
unused opcode 7-6
IREQ bit (Interrupt Request)
Poll Register 7-26
Poll Status Register 7-25
IRQ signal (Slave Interrupt Request)
definition 3-6
L
L2-L0 field (Interrupt Type) 7-35
LB2-LB0 field (Lower Boundary) 5-4
LCS signal (Lower Memory Chip Select)
definition 3-6
LOOP bit (Loopback) 10-2
Low Memory Chip Select Register
description 5-6
LTM bit (LevelTriggered Mode)
INT0 Control Register 7-13
INT1 Control Register 7-13
INT2 Control Register 7-15
INT3 Control Register 7-15
INT4 Control Register 7-16
M
M/IO bit (Memory/I/O Space) 4-4
M6-M0 field (MCS Block Size) 5-10
M6-M0 field (Refresh Base) 6-1
MA15-MA7 signals (Multiplexed Address Bus)
definition 3-2
Maskable interrupts 7-2
Master mode interrupt registers 7-12
Master mode operation 7-9
MC bit (Maximum Count Bit)
Timer 0 Mode/Control Register 8-3
Timer 1 Mode/Control Register 8-3
Timer 2 Mode/Control Register 8-5
MCS2-MCS0 signals (Midrange Memory Chip Selects
2-0)
definition 3-7
MCS3 signal (Midrange Memory Chip Select 3)
definition 3-7
Memory Partition Register
description 6-1
Midrange Memory Chip Select Register
description 5-8
MS bit (Memory/I/O Space Selector) 5-11
MSK (interrupt mask bit) 7-2
MSK bit (Interrupt Mask)
DMA Interrupt Control Registers 7-17
Timer Interrupt Control Registers 7-17
MSK bit (Mask)
DMA Interrupt Control Registers 7-29
INT0 Control Register 7-13
Index
I-5