AMD AM186EM User Manual page 37

MCS3/RFSH Midrange Memory Chip Select 3
(output, synchronous, internal pullup)
Automatic Refresh (output, synchronous)
MCS3—This pin indicates to the system that a memory access is in
progress to the fourth region of the midrange memory block. The base
address and size of the midrange memory block are programmable.
MCS3 is held High during a bus hold condition. In addition, this pin has
a weak internal pullup resistor that is active during reset.
RFSH—This pin provides a signal timed for auto refresh to PSRAM
devices. It is only enabled to function as a refresh pulse when the
PSRAM mode bit is set in the LMCS register. An active Low pulse is
generated for 1.5 clock cycles with an adequate deassertion period to
ensure overall auto refresh cycle time is met.
MCS2–MCS0 Midrange Memory Chip Selects
(output, synchronous, internal pullup)
These pins indicate to the system that a memory access is in progress
to the corresponding region of the midrange memory block. The base
address and size of the midrange memory block are programmable.
MCS2–MCS0 are held High during a bus hold condition. In addition,
they have weak internal pullup resistors that are active during a reset.
NMI Nonmaskable Interrupt (input, synchronous, edge-sensitive)
This pin indicates to the microcontroller that an interrupt request has
occurred. The NMI signal is the highest priority hardware interrupt and,
unlike the INT4–INT0 pins, cannot be masked. The microcontroller
always transfers program execution to the location specified by the
nonmaskable interrupt vector in the microcontroller interrupt vector
table when NMI is asserted.
Although NMI is the highest priority interrupt source, it does not
participate in the priority resolution process of the maskable interrupts.
There is no bit associated with NMI in the interrupt in-service or interrupt
request registers. This means that a new NMI request can interrupt an
executing NMI interrupt service routine. As with all hardware interrupts,
the IF (interrupt flag) is cleared when the processor takes the interrupt,
disabling the maskable interrupt sources. However, if maskable
interrupts are re-enabled by software in the NMI interrupt service
routine, via the STI instruction for example, the fact that an NMI is
currently in service will not have any effect on the priority resolution of
maskable interrupt requests. For this reason, it is strongly advised that
the interrupt service routine for NMI does not enable the maskable
interrupts.
An NMI transition from Low to High is latched and synchronized
internally, and it initiates the interrupt at the next instruction boundary.
To guarantee that the interrupt is recognized, the NMI pin must be
asserted for at least one CLKOUTA period.
PCS3–PCS0 Peripheral Chip Selects (output, synchronous)
These pins indicate to the system that a memory access is in progress
to the corresponding region of the peripheral memory block (either I/O
or memory address space). The base address of the peripheral memory
block is programmable. PCS3–PCS0 are held High during a bus hold
System Overview
3-7