Table 1.1 Data Protection For Components And Interfaces - Fujitsu GP 7000F Manual

High-speed I/O interface
 One built-in 40 MB/s UltraSCSI Single-Ended interface for internal devices.
 One built-in 100BASE-TX interface (10/100 Mbps, auto-sensing).
 The GP7000F has some 64-bits PCI (Peripheral Component Interconnect) buses.
 Additional interfaces, such as 100BASE-TX, FDDI, ATM, can be provided by installing PCI
cards. Both short and long size PCI cards can be installed. (*1)
*1)
High-performance, Large-capacity File Devices
 Up to 22, 7200rpm or 10000rpm, UltraSCSI disk drives can be built in. Note that the number of
drives that can be installed depends on each model.
 The disk drives can be hot-swappable
 One CD-ROM drive unit is provided as standard.
 One tape drive can be built in as optional.
Reliability, Availability, and Serviceability (RAS) features
 Error Correction Code (ECC) is implemented for on-chip cache, external cache, memory
module and data paths. The data for the I/O data path(PCI) is protected by parity.

Table 1.1 Data Protection for Components and Interfaces

Components and interfaces
Processor (on-chip & external cache)
Memory
Data path
Address path
I/O bus (PCI)
Processor operation
Built-in basic SCSI, LAN, parallel
Note:
 Power-on diagnostics are executed on the system components, such as processors, memory
modules and so on, during initial power-on or reset of the system.
 Automatic System Reconfiguration (ASR) isolates faulty hardware components immediately
after detecting it. The ASR function isolates not only faulty components detected during initial
power-on but also those detected while the system is running. However, the ASR function
cannot restart the system if errors are detected in the resources required for booting up the
system, or in the basic components of the system.
The maximum length of the cards that can be installed in PCI slots #8 to #12 of the
M600R Main cabinet is 19.4cm.
The RS232C interface and a floppy disk on a standard configuration are not
protected by parity.
Data protection method
By ECC (corrects 1 bit and detects 2 bit)
By ECC (corrects 1 bit and detects 2 bit)
By ECC (corrects 1 bit and detects 2 bit)
By parity
By parity
Operation monitoring by an independent
processor
By parity, IP check sum
1.1 Key Features
3