Signal Block Diagram (A-Pcb) - Panasonic PT-RS30K Service Manual

SECTION 4 SCHEMATIC DIAGRAMS

1.5. Signal Block Diagram (A-PCB)

A-P.C.Board
IC3072 SDI_EQ_SCK/SDI_EQ_SDO
JK3008
CABLE EQUALIZER
SDI_EQ_SDI
SDI-IN1
SDI
SID
SDI_EQ_SS
SDI_EQ_CDN/3GEQ_SDO_P/3GEQ_SDO_N
IC3071
SDI_EQ_SCK/SDI_EQ_SDO
JK3009
CABLE EQUALIZER
SDI_EQ_SDI
SDI-IN2
SDI
SID
SDI_EQ_SS2
SDI_EQ_CDN2/3GEQ_SDO_P2/3GEQ_SDO_N2
JK3001
RGB1-IN R/Pr/Video
Q3036, BUFFER
G/Y
Y/C(Gch/Bch) Q3037, BUFFER
B/Pb/C
Q3038, BUFFER
VIDEO(Rch)
H/V
TMDS
DVI D-IN
50SCL14
50SDA14
IC3068
SW
IC3067
JK3005
EEPROM(EDID)
R
Q3033, Bu er
G
Q3034, Bu er
RGB 2-IN
B Q3035, Bu er
H/V
IC3063
SW
50SCL14
50SDA14
IC3061 LEVEL SHIFT
EEPROM(EDID) Q3029,Q3030
JK3006
8
TMDS
HDMI
HDMI1_SDA
HDMI1_SCL EDID_33SCL
EDID_33SDA
JK2001
T2001
LAN
8 8
TRANS
DIGITAL LINK
IC2003
EEPROM
3
4
3
4
CVBS
IC3075 IC3062
G(for C.C.) C
SEL.SW
VIDEO AMP
Y
IC3020
CC_SELA/CC_SELB
R
G
3ch-ADC
SOG
B
HV FREQUENCY DET.
B
PICTURE ADJ
・CONTRAST
G
SOG
R
IC3064
B0～B9
SW
R0～R9
G0～G9
ACT
HD
VD
PICLK
HDCP Key
EEPROM
IC3010
B CLK245(24.576MHz)
G
3ch-ADC
SOG
R
B0～B9
R R0～R9
G0～G9
G ACT
HD
SOG
VD
B
PICLK
IC3065
HV FREQUENCY DET.
PICTURE ADJ
SW
HDMI RxD
33CPUSCL2_A1
33CPUSDA2_A1
HDCP Key
8 EEPROM
TMDS
2
AH_TMDS_SDA
EDID control
AH_TMDS_SCL
EDID_33SCL
EDID_33SDA
IC2001 HDBTMC_TXD
HDBTMC_RXD
33CPUSCL2
IC3731
33CPUSDA2
HDBT_CFG_SCL
LAMP1_SCL
HDBT_CFB_SDA
SEL.SW LAMP1_SDA
HD BaseT LAMP2_SCL
TRANSMITTER/ LAMP2_SDA
RECEIVER
SPI
33CPUSCL2_A1
IC3736
33CPUSDA2_A1
SEL.SW
IC3751 33CPUSCL2_A2
SDI/SCL
33CPUSDA2_A2
33CPUSDA4
33CPUSCL4
3-AXIS MOTION
SCL_COLOR
SDA_COLOR
SENSOR
HDBT_IR<TO IC3501>
HDBT_IR_SUB<TO A2>
CLK245(24.576MHz)
IC3058
SDI_EQ_SCK/SDI_EQ_SDO
FPGA1
SDI_EQ_SDI
SDI_EQ_SS
SDI_EQ_CDN/3GEQ_SDO_P/3GEQ_SDO_N
SDI_EQ_SS2
SDI_EQ_CDN2/3GEQ_SDO_P2/3GEQ_SDO_N2
INPUT SELECT
34 TEST PATTERN
APL DET. (IRIS/AI)
PICTURE POSITION ADJ
(H-SHIFT)
CHROMA DET.
(DYNAMIC RGB BOOSTER)
SDI RECEIVER
33CPUSCL2_A2
33CPUSDA2_A2 (GTP TRANSCEIVER)
34 ・SDI DECODE
・FAN I/O
・LENS I/O
・SHUTTER I/O
FP1_FP2_SCLK
FP1_FP2_NCS
FP1_FP2_SO
FP1_FP2_SI
FP1_FP2_INT_SYNC
FP1_FP2_EXT_SYNC
DIA-6
IC3501
CPU & IP/RESIZE
CVBS or G(for C.C.)
C VIDEO DECODER
2D COMB
Y
CLK245(24.576MHz)
RESIZE
PICTURE POSITION ADJ
(V-SHIFT)
PICTURE ADJ
・BRIGHTNESS
・CONTRAST
・COLOR
・TINT
・SHARPNESS
33CPUSDA1
KEYSTONE
33CPUSCL1
(VERTICAL)
3D NR
34
IP (SD/HD)
P IN P
34
CPU
CPU_FPGA1_CS
SYSTEM CONTROL
CPU_CFG_PROG1
・LAMP/BALLAST Cont.
CPU_CFG_DONE12 ・FAN MOTOR Cont.
・LENS MOTOR Cont.
CPU_FPGA_CLK1
・SHUTTER MOTOR Cont.
CPU_FPGA_SO1 ・LAN Cont.
CPU_FPGA_SI
CPU_FPGA_RST
CPU_FPGA_RW
EDID_33SCL
EDID_33SDA
HDBTMC_TXD
HDBTMC_RXD
33CPUSCL2
33CPUSDA2
33CPUSDA4
33CPUSCL4
CPUIICSEL3
CPUIICSEL4
CPUIICSEL1 HDBT_IR<FROM IC2001>
CPUIICSEL2
CPU_CFG_DONE12
IC3761 IC3762
CPU_FPGA_CLK
BUFFER BUFFER
IC3771 IC3772
CPU_FPGA_SO0
BUFFER BUFFER
A1
+3.3V STB
+5V STB
To PB-P.C.Board
+3.3V_A
(PB3)
+3.3V_B
+12V
X3501
Clock Gen.
(35.455MHz)
IC3901,IC3921,
IC3941,IC3961
DDR3 SDRAM
IC3716
128M FLASH
MAIN SOFT
IC3721
SDRAM
IC3741
RTC
IC3711
EEPROM
A2 To DG-P.C.Board
IC3712
EEPROM (DG2)
LVDS 44
CASE_OPEN(65)
PWR_DOWN(62)
AC_90V_DET(63)
CPU_BLST1(75)
For LD control
CPU_BLST2(76)
X2_232CIN_TXD(95)
X2_232CIN_RXD(96)
RS232C-IN PORT
232COUT_TXD(97)
232COUT_RXD(98)
RS232C-OUT PORT
R8_TXD(4)
R8_RXD(5)
SUB CPU
REQ_TO_R8(6)
CPU_CFG_PROG2(80)
SCX2-->FPGA2
CPU_FPGA2_CS(81)
CONFIG
IRIN_FRONT(1)
IRIN_REAR(2) X2_IR
HDBT_IR_SUB(3) FRONT/REAR/HDBT
CPU_CFG_DONE12(79)
CPU_FPGA_CLK2(83)
SCX2-->FPGA2 Serial I/F
CPU_FPGA_SO2(85)
CPU_FPGA_SI(86)
CPU_FPGA_RST(87)
CPU_FPGA_RW(88)
LAMP1_SCL(69)
LAMP1_SDA(70)
LAMP2_SCL(72)
For CPLD update use
LAMP2_SDA(73)
FP1_FP2_INT_SYNC(116)
3DSYNC CONTROL
FP1_FP2_EXT_SYNC(118)
FP1_FP2_SI(119)
FP1_FP2_SO(117)
FPGA1-FPGA2 Serial I/F
FP1_FP2_NCS(115)
FP1_FP2_SCLK(114)
SCL_COLOR(90)
SDA_COLOR(91) COLOR SENSOR /
PRESSURE SENSOR
HDBT232C_TXD(110)
HDBT232C_RXD(111) HDBT_TX/RX