Status Register - Motorola DigitalDNA MPC180E User Manual

Arc Four Execution Unit Registers

5.1.1 Status Register

The AFEU Status Register, shown in Figure 5-1, contains seven bits of information. These
bits describe the state of the AFEU circuit and are all active-high.
0 24
Field —
Reset
R/W
Addr
Figure 5-1. Arc Four Execution Unit Status Register
Table 5-2 describes the AFEU Status Register fields.
Table 5-2. AFEU Status Register Field Descriptions
Bit Name
0–24 —
25 Input Buffer empty
26 Full message done
27 Sub-message done
28 Permute done
29 Initialize done
30 IRQ
31 Busy
5-2
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
25 26
Input Buffer Full msg
empty done
0000_0000_0000_0000
Reserved, should be cleared.
Set when there is no data waiting in the AFEU Input Buffer. This can be used to monitor
when the AFEU is ready to receive the next sub-message while it is processing the
current sub-message. Writing to the Message register will clear this bit.
Set when the last sub-message has been processed. This bit will remain set until a new
key is written. Reading from the Cipher register will clear this bit.
Set when the sub-message has been processed. Once the next sub-message is written,
the AFEU will begin processing it and this bit will clear.
Set once the memory is permuted with the key. Once the first sub-message is written, the
AFEU will begin processing the message and this bit will clear.
Set once memory initialization is complete. Once the key data and length is written, the
AFEU will begin permuting the memory and this bit will clear.
Asserted whenever an interrupt is pending (if interrupts are enabled). The following
conditions will generate an interrupt:
Memory initialization done
Memory permutation done
Sub-Message processing done
Full Message processing done
The specific cause of the interrupt can be determined by reading the additional bits of the
status register.
Hardware interrupts are disabled following a reset. The IRQ bit in the status register is not
affected by masking hardware interrupts in the control register.
Asserted whenever the AFEU core is not in an idle state. Memory initialization or
permutation and message processing conditions will cause this bit to be set. The Busy bit
will be set during context writes/reads.
MPC180E Security Processor User's Manual
27 28 29
Sub-msg Permute Initialize
done done done
Read
0x401
Description
30 31
IRQ Busy