Imask Register - Motorola DigitalDNA MPC180E User Manual

External Bus Interface
0
Field
Reset
R/W
16 17
Field DEU AFEU
Reset 0 001
R/W
Addr
Table 3-4 describes the ID fields.
Bits Name
0–7 — Reserved, should be cleared.
8–10 MPC180E MPC180E version number.
11–13 MDEU Message Digest Execution Unit version number
14–16 DEU Data Encryption Standard Execution Unit version number
17–19 AFEU Arc Four Execution Unit version number
20–22 RNG Random Number Generator version number
23–25 — Reserved, should be cleared.
26–28 EBI Controller version number
29–31 PKEU Public key Execution Unit version number

3.3.1.3 IMASK Register

The built-in interrupt controller (IRQ module) gathers all execution unit interrupt signals
and presents one output (IRQ) to the host. It also lets the user selectively mask or disable
interrupts from execution units by programming the IMASK register. In this way, interrupts
can be controlled from a single source. Some execution-unit-specific configuration is
required to ensure proper response to any interrupt. The user can read the appropriate
address in CSTAT to get the interrupt status of all execution units at once.
The interrupt port consists of the IRQ output, which is negated after the host responds to
all pending interrupts from the execution units.
All interrupts from the execution units have the same priority. Figure 3-4 shows the bit
assignments in the IRQ register for all the MPC180E execution units. All enable (mask)
registers operate on the corresponding bits. An interrupt is masked when its corresponding
IMASK bit is a 1.
3-8
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
7
—
0000_0000
19 20 22 23
RNG
001
Figure 3-3. ID Register
Table 3-4. ID Field Descriptions
MPC180E Security Processor User's Manual
8 10 11
MPC180E
010
Read
25 26
— EBI
0_10 01_0
Read
0x901
Description
13 14 15
MDEU DEU
0_01 01
28 29 31
PKEU
00x