S-Box I/J Register; S-Box0 - S-Box63 Memory - Motorola DigitalDNA MPC180E User Manual

Arc Four Execution Unit Registers

5.1.9 S-box I/J Register

The Sbox I/J Register is a 24-bit read/write register where the Sbox I/J pointers are stored.
The contents of this register must be read prior to context switching and must be written
back to the AFEU before resuming message processing of an interrupted message. This
register may be accessed whenever the AFEU is idle.
5.1.10 S-box0 – S-box63 Memory
The S-box Memory consists of 64 read/write 32-bit blocks. The entire contents of the S-box
memory must be read prior to context switching and must be written back to the AFEU
before resuming message processing of an interrupted message. The S-box memory may
be accessed whenever the AFEU is idle.
Chapter 5. Arc Four Execution Unit 5-5
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE