Table Of Contents - Motorola DigitalDNA MPC180E User Manual

Paragraph
Number
1.1 Features ............................................................................................................... 1-1
1.2 System Architecture............................................................................................ 1-2
1.3 Architectural Overview....................................................................................... 1-3
1.3.1 Public Key Execution Unit (PKEU) ............................................................... 1-4
1.3.2 Data Encryption Standard Execution Unit (DEU).......................................... 1-4
1.3.3 Arc Four Execution Unit (AFEU) .................................................................. 1-5
1.3.4 Message Digest Execution Unit (MDEU) ...................................................... 1-5
1.3.5 Random Number Generator (RNG)................................................................ 1-5
1.3.6 Interrupt Controller (IRQ) .............................................................................. 1-5
2.1 Signal Descriptions ............................................................................................. 2-1
External Bus Interface and Memory Map
3.1 Execution Unit Registers .................................................................................... 3-1
3.2 Address Map ....................................................................................................... 3-2
3.3 External Bus Interface......................................................................................... 3-4
3.3.1 EBI Registers .................................................................................................. 3-5
3.3.1.1 Command/Status Register (CSTAT) .......................................................... 3-5
3.3.1.2 ID Register.................................................................................................. 3-7
3.3.1.3 IMASK Register ......................................................................................... 3-8
3.3.1.4 Input Buffer Control (IBCTL) and Output Buffer Control
(OBCTL) Registers................................................................................. 3-9
3.3.1.5 Input Buffer Count (IBCNT) and Output Buffer Count
3.3.1.6 (OBCNT) Registers .................................................................................. 3-11
3.4 EBI Controller Operation.................................................................................. 3-11
3.4.1 Buffer Accesses (FIFO Mode)...................................................................... 3-12
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
CONTENTS
Title
Chapter 1
Overview
Chapter 2
Signal Descriptions
Chapter 3
Contents
Page
Number
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