System Management Bus (Smbus) Interface - Intel 855PM Design Manual

Platform Design Checklist
14.8.4.

System Management Bus (SMBus) Interface

Pin Name
INTRUDER#
SMBALERT#/ Pull up to V3ALWAYS
GPIO[11]
SMBCLK Pull up to V3ALWAYS
SMBDATA
SMLINK[1:0] Pull up to V3ALWAYS
310
ICH4-M System Management Interface – Resistor Recommendations
System
Pull up/Pull down
Pull up to VccRTC 10 k
10 k
See Notes
See Notes
Notes
RTC well input requires pull up to reduce leakage from
coin cell battery in G3.
Requires external pull up resistors. Pull up value is
determined by bus section characteristics. Additional
circuitry may be required to connect high and low
powered sections.
Resistor change for faster rise time and to ensure
timings are within specification. Value of pull up resistor
is also determined by line load.
Intel CRB uses 10K pull up resistor. Please see Intel
CRB schematics page 18.
The SMBus and SMLink signals must be tied together
externally in S0 for SMBus 2.0 compliance:
SMBCLK connects to SMLink[0]
SMBDATA connects to SMLink[1]
Requires external pull up resistors. Pull up value is
determined by bus section characteristics. Additional
circuitry may be required to connect high and low
powered sections.
Resistor change for faster rise time and to ensure
timings are within specification. Value of pull up resistor
is also determined by line load.
Intel CRB uses 4.7 k pull up resistor. Please see Intel
schematics page 18.
The SMLink and SMBus signals must be tied together
externally in S0 for SMBus 2.0 compliance:
SMLink[0] connects to SMBCLK
SMLink[1] connects to SMBDATA
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Intel 855PM Chipset Platform Design Guide
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