Ddr Vtt High Frequency And Bulk Decoupling; Agp Decoupling; Hub Interface Decoupling; Fwh Decoupling - Intel 855PM Design Manual

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11.7.4.

DDR VTT High Frequency and Bulk Decoupling

The VTT Island must be decoupled using high-speed bypass capacitors, one 0603, 0.1-µF capacitor per
two DDR signals. These decoupling capacitors connect directly to the VTT island and to ground, and
must be spread out across the termination island so that all the parallel termination resistors are near
high frequency capacitors. The capacitor ground via should be as close to the capacitor pad as possible,
within 25 mils with as thick a trace as possible. The ground end of the capacitors must connect to the
ground flood on Layer 2 and to the ground plane on Layer 3 through a via. Finally, the distance from
any DDR termination resistor pin to a VTT capacitor pin must not exceed more then 100 mils.
11.7.5.

AGP Decoupling

See Section 7.3.4 for details.
11.7.6.

Hub Interface Decoupling

See Section 8.5 for details.
11.7.7.

FWH Decoupling

A 0.1-µF capacitor should be placed between the VCC supply pins and the VSS ground pins to decouple
high frequency noise, which may affect the programmability of the device. Additionally, a 4.7-µF
capacitor should be placed between the VCC supply pins and the VSS ground pins to decouple low
frequency noise. The capacitors should be placed no further than 390 mils from the VCC supply pins.
11.7.8.

General LAN Decoupling

All VCC pins should be connected to the same power supply.
All VSS pins should be connected to the same ground plane.
Four to six decoupling capacitors, including two 4.7-µF capacitors are recommended
Place decoupling as close as possible to power pins.
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Intel 855PM Chipset Platform Design Guide
Platform Power Delivery Guidelines
267