Trace Length Mismatch Requirements; Table 39. Layout Routing Guidelines For Agp 2X/4X Signals; Table 40. Agp 2.0 Data Lengths Relative To Strobe Length - Intel 855PM Design Manual

AGP Port Design Guidelines

Table 39. Layout Routing Guidelines for AGP 2X/4X Signals

Signal
2X/4X Timing
Domain Set#1
2X/4X Timing
Domain Set#2
2X/4X Timing
Domain Set#3
7.3.2.3.

Trace Length Mismatch Requirements

Table 40. AGP 2.0 Data Lengths Relative to Strobe Length

Max Trace Length
< 6 in
The trace length minimum and maximum (relative to strobe length) should be applied to each set of
2X/4X timing domain signals independently . That is, if AD_STB0 and ADSTB0# are 5 inches, then
AD[15:0] and C/BE[1:0] must be between 4.9 inches and 5.1 inches. However AD_STB1 and
ADSTB1# can be 3.5 inches (and therefore AD[31:16] and C/BE#[3:2] must be between 3.4 inches and
3.6 inches). In addition, all 2X/4X timing domain signals must meet the maximum trace length
requirements.
All signals should be routed as strip lines (inner layers).
All signals in a signal group should be routed on the same layer. Routing studies have shown that
these guidelines can be met. The trace length and trace spacing requirements must not be violated
by any signal. Trace length mismatch for all signals within a signal group should be as close to 0
inches as possible to provide optimal timing margin.
Table 41 shows the AGP 2.0 routing summary.
172
Trace Space
Maximum
(mils)
Length (inch)
(4 mil traces)
6 8
6 8
6 8
Trace Spacing Strobe Length
1:2
Length
Mismatch Relative To
(inch)
± 0.1 AGP_ADSTB0 and
AGP_ADSTB0#
± 0.1 AGP_ADSTB1 and
AGP_ADSTB1#
± 0.1 AGP_SBSTB and
AGP_SBSTB #
Min Trace Length
X X – 0.1 in
®
Intel 855PM Chipset Platform Design Guide
R
Notes
AGP_ADSTB0,
AGP_ADSTB0# must
be the same length
(±10 mils)
AGP_ADSTB1,
AGP_ADSTB1# must
be the same length
(±10 mils)
AGP_SBSTB,
AGP_SBSTB# must be
the same length (±10
mils)
Max Trace Length
X + 0.1 in