Ide Interface (Secondary Ide Connector) - Intel 855PM Design Manual

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14.8.13. IDE Interface (Secondary IDE Connector)

Pin Name
Pull up/Pull down
SDD[15:0]
SDA[2:0],
SDCS1#,
SDCS3#,
SDDACK#,
SDIOW#, SDIOR#
SDDREQ
SIORDY Pull up to Vcc3_3
PCI_RST#
Mobile IDE Swap
Bay Support
®
Intel 855PM Chipset Platform Design Guide
ICH4-M IDE Interface – Resistor Recommendations
System
None
None
None
4.7 k
Series
Damping
No extra series termination resistors or other
pull ups/pull downs are required. These signals
have integrated series resistors.
PDD7/SDD7 does not require a 10 KΩ pull
down resistor.
NOTE: Simulation data indicates that the
integrated series termination resistors are a
nominal 33 Ω but can range from 31 Ω to 43 Ω.
Refer to ATA ATAPI-4 specification.
No extra series termination resistors. Pads for
series resistors can be implemented should the
system designer have signal integrity concerns.
These signals have integrated series resistors.
NOTE: Simulation data indicates that the
integrated series termination resistors are a
nominal 33 but can range from 31 to 43 .
No extra series termination resistors.
No pull down resistors needed.
This signal has integrated series resistors in
the ICH4-M.
This signal has integrated pull down resistors in
the ICH4-M.
This signal has integrated series resistor in the
ICH4-M
22 - 47 The signal must be buffered to form IDE_RST#
for improved signal integrity.
See Section 9.1.4 contains recommendations
for implementating the ICH4-M's IDE interface
tri-state feature. This feature can be used for
systems designed to support an IDE "hot" swap
drive bay.
Platform Design Checklist
Notes
321