Table 29. Command Topology 2 Routing Guidelines - Intel 855PM Design Manual

R
pairs SCK/SCK#[5:0]. Command signals should be routed on inner layers with minimized external trace
lengths.

Table 29. Command Topology 2 Routing Guidelines

Signal Group
Motherboard Topology
Reference Plane
Characteristic Trace Impedance (Zo)
Trace Width
Trace to Space ratio
Group Spacing
Trace Length L1 – MCH Command Signal Ball to
Series Resistor 1 Pad
Trace Length L2 – Series Resistor Pad to First
SO-DIMM Pad
Trace Length L3 – Series Resistor Load to
Second SO-DIMM Pad
Trace Length L4 – Second SO-DIMM Pad to
Parallel Resistor Pad
Series Termination Resistor (Rs)
Parallel Termination Resistor (Rt)
Maximum Recommended Motherboard Via
Count Per Signal
Length Matching Requirements
NOTES:
Recommended resistor values and trace lengths may change in a later revision of the design guide.
1.
Power distribution vias from Rt to Vtt are not included in this count.
2.
The overall maximum and minimum length to the SO-DIMM must comply with clock length matching
3.
requirements.
It is possible to route using 3 vias if one via is shared that connects L1, L3, and series termination and if one via
4.
is shared that connects to the SO-DIMM1 pad and parallel termination resistor.
L1 trace length does not include MCH package length and should not be used when calculating L1 length.
5.
®
Intel 855PM Chipset Platform Design Guide
Parameter
System Memory Design Guidelines (DDR-SDRAM)
Routing Guidelines
Command – SMA[12:0], SBS[1:0], SRAS#,
SCAS#, SWE#
Daisy Chain with Parallel Termination
Ground Referenced
55 ± 15%
Inner layers: 4 mils
Outer layers: 5 mils
1:2 (e.g. 4 mil trace to 8 mil space)
Isolation spacing for non-DDR related
signals = 20 mils minimum
Min = 0.5 inches
Max = 5.0 inches
Max = 1.0 inches
Min = 0.4 inches
Max = 1.75 inches
Max = 0.25 inches
10 ± 5%
56 ± 5%
6
Command Signals to SCK/SCK#[5:0]
See Section 6.1.3.2.2 for details
Figure Notes
1
Figure 82 3, 5
Figure 82 3
Figure 82 3
Figure 82
2, 4
145