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Electrical Specifications
Figure 8. SSP AC Timing Definitions
SCLK_C
SFRM_C
TXD_C
RXD_C
Table 24. SSP AC Timing Specifications
Symbol
Tsfmv
Trxds
Trxdh
Tsfmv
4.9.3
Boundary Scan Test Signal Timings
Table 25, "Boundary Scan Test Signal Timing"
Table 25. Boundary Scan Test Signal Timing (Sheet 1 of 2)
Symbol
TBSF
TBSCH
TBSCL
TBSCR
TBSCF
TBSIS1
TBSIH1
TBSIS2
TBSIH2
TBSOV1
TOF1
TOV12
38
Description
SCLK_C rise to SFRM_C driven valid
RXD_C valid to SCLK_C fall (input setup)
SCLK_C fall to RXD_C invalid (input
hold)
SCLK_C rise to TXD_C valid
Parameter
TCK frequency
TCK high time
TCK low time
TCK rise time
TCK fall time
Input setup to TCK TDI, TMS
Input hold from TCK TDI, TMS
Input setup to TCK nTRST
Input hold from TCK nTRST
TDO valid delay
TDO float delay
All outputs (non-test) valid delay
Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification
T sfmv
T sfmv
T rxds
Min
11
0
shows the boundary scan test signal timing.
Min
Max
Units
0.0
33.33
MHz
15.0
ns
15.0
ns
5.0
ns
5.0
ns
4.0
ns
6.0
ns
25.0
ns
3.0
ns
1.5
6.9
ns
1.1
5.4
ns
1.5
6.9
ns
T rxdh
A4774-01
Max
Units
21
ns
ns
ns
22
ns
Notes
Measured at 1.5 V
Measured at 1.5 V
0.8 V to 2.0 V
2.0 V to 0.8 V
Relative to falling edge of TCK
Relative to falling edge of TCK
Relative to falling edge of TCK
Notes
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