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A.1.37. PWRGOOD (I)
The PWRGOOD (Power Good) signal is a 2.5V tolerant processor input. The processor
requires this signal to be a clean indication that the clocks and power supplies (Vcc
etc.) are stable and within their specifications. Clean implies that the signal will remain low
(capable of sinking leakage current), without glitches, from the time that the power supplies
are turned on until they come within specification. The signal must then transition
monotonically to a high (2.5V) state. Figure A-1 illustrates the relationship of PWRGOOD to
other system signals. PWRGOOD can be driven inactive at any time, but clocks and power
must again be stable before a subsequent rising edge of PWRGOOD. It must also meet the
minimum pulse width specification in Table 7-12 and be followed by a 1 ms RESET# pulse.
The PWRGOOD signal must be supplied to the processor as it is used to protect internal
circuits against voltage sequencing issues. The PWRGOOD signal does not need to be
synchronized for FRC operation. It should be driven high throughout boundary scan
operation.
A.1.38. REQ[4:0]# (I/O)
The REQ[4:0]# (Request Command) signals must connect the appropriate pins of all Pentium
II processor system bus agents. They are asserted by the current bus owner over two clock
cycles to define the currently active transaction type.
BCLK
V
,
CC
CORE
V
CC
L2
PWRGOOD
RESET#
Clock Ratio
Figure A-1. PWRGOOD Relationship at Power-On
A.1.39. RESET# (I)
Asserting the RESET# signal resets all processors to known states and invalidates their L1
and L2 caches without writing back any of their contents. RESET# must remain active for
one microsecond for a "warm" reset; for a power-on reset, RESET# must stay active for at
SIGNALS REFERENCE
CORE
1 ms
000760b
A-11
,
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