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CHAPTER 14
ADVANCED FEATURES
14.1.
ADDITIONAL INFORMATION ................................................................................14-1
APPENDIX A
SIGNALS REFERENCE
Figure
1-1.
Second Level Cache Implementations ................................................................. 1-2
2-1.
Three Engines Communicating Using an Instruction Pool..................................... 2-1
2-2.
A Typical Pseudo Code Fragment........................................................................ 2-2
2-3.
The Three Core Engines Interface with Memory via Unified Caches ..................... 2-3
2-4.
Inside the Fetch/Decode Unit ............................................................................... 2-4
2-5.
Inside the Dispatch/Execute Unit.......................................................................... 2-5
2-6.
Inside the Retire Unit ........................................................................................... 2-7
2-7.
Inside the Bus Interface Unit ................................................................................ 2-8
2-8.
Out of Order Core and Retirement Pipeline.........................................................2-10
2-9.
Out-of-Order Core and Retirement Pipeline ........................................................2-12
3-1.
Latched Bus Protocol........................................................................................... 3-1
5-1.
Hardware Configuration Signal Sampling ............................................................. 5-1
6-1.
Simplified Block Diagram of Processor TAP Logic ................................................ 6-2
6-2.
TAP Controller Finite State Machine .................................................................... 6-3
6-3.
Processor TAP Instruction Register ..................................................................... 6-5
6-4.
Operation of the Processor TAP Instruction Register............................................ 6-5
6-5.
TAP Instruction Register Access .......................................................................... 6-6
7-1.
GTL+ Bus Topology............................................................................................. 7-1
7-2.
Stop Clock State Machine.................................................................................... 7-2
7-3.
Timing Diagram of Clock Ratio Signals................................................................. 7-7
7-4.
Example Schematic for Clock Ratio Pin Sharing................................................... 7-8
7-5.
BCLK to Core Logic Offset..................................................................................7-25
7-6.
BCLK, PICCLK, TCK Generic Clock Waveform...................................................7-25
7-7.
System Bus Valid Delay Timings.........................................................................7-26
7-8.
System Bus Setup and Hold Timings ..................................................................7-26
7-9.
FRC Mode BCLK to PICCLK Timing ...................................................................7-27
7-10.
System Bus Reset and Configuration Timings.....................................................7-27
7-11.
Power-On Reset and Configuration Timings........................................................7-28
7-12.
Test Timings (TAP Connection) ..........................................................................7-29
7-13.
Test Reset Timings.............................................................................................7-29
8-1.
Example Terminated Bus with GTL+ Transceivers ............................................... 8-2
8-2.
Receiver Waveform Showing Signal Quality Parameters...................................... 8-3
8-3.
Low to High GTL+ Receiver Ringback Tolerance ................................................. 8-5
8-4.
Standard Input Hi-to-Lo Waveform for Characterizing Receiver
Ringback Tolerance ............................................................................................. 8-6
8-5.
Measuring Nominal Flight Time............................................................................ 8-8
8-6.
Flight Time of a Rising Edge Slower than 0.3V/ns ................................................ 8-9
8-7.
Extrapolated Flight Time of a Non-Monotonic Rising Edge ..................................8-10
8-8.
Extrapolated Flight Time of a Non-Monotonic Falling Edge ..................................8-11
8-9.
Test Load for Measuring Output AC Timings.......................................................8-15
8-10.
Clock to Output Data Timing (T CO ) ....................................................................8-15
Figures
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