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ELECTRICAL SPECIFICATIONS
®
7.12. PENTIUM
II PROCESSOR SYSTEM BUS AC
SPECIFICATIONS
The system bus timings specified in this section are defined at the processor edge fingers.
Unless otherwise specified, timings are tested at the processor core during manufacturing.
Timings at the processor edge fingers are specified by design characterization. See Appendix
A for the Pentium II processor edge finger signal definitions.
Table 7-9 through Table 7-14 list the AC specifications associated with the Pentium II
processor system bus. The system bus AC specifications are broken into the following
categories: Table 7-9 and Table 7-10 contain the system bus clock core frequency and cache
bus frequencies; Table 7-11 contains the GTL+ specifications; Table 7-12 contains the
CMOS signal group specifications; Table 7-13 contains timings for the reset conditions;
Table 7-14 covers APIC bus timing; and Table 7-15 covers TAP timing.
All system bus AC specifications for the GTL+ signal group are relative to the rising edge of
the BCLK input. All GTL+ timings are referenced to V
for both '0' and '1' logic levels
REF
unless otherwise specified.
The timings specified in this section should be used in conjunction with the I/O buffer
models provided by Intel. These I/O buffer models, which include package information, are
available in IBIS format on Intel's web site: http://www.intel.com. GTL+ layout guidelines
®
are also available in AP-585, Pentium
II Processor GTL+ Guidelines (Order Number
243330).
Care should be taken to read all notes associated with a particular timing parameter.
7-19
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