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SIGNALS REFERENCE
A.1.11. BPM[1:0]# (I/O)
The BPM[1:0]# (Breakpoint Monitor) signals are breakpoint and performance monitor
signals. They are outputs from the processor which indicate the status of breakpoints and
programmable counters used for monitoring processor performance.
A.1.12. BPRI# (I)
The BPRI# (Bus Priority Request) signal is used to arbitrate for ownership of the Pentium II
processor system bus. It must connect the appropriate pins of all Pentium II processor system
bus agents. Observing BPRI# active (as asserted by the priority agent) causes all other agents
to stop issuing new requests, unless such requests are part of an ongoing locked operation.
The priority agent keeps BPRI# asserted until all of its requests are completed, then releases
the bus by deasserting BPRI#.
A.1.13. BR0# (I/O), BR1# (I)
The BR0# and BR1# (Bus Request) pins drive the BREQ[1:0]# signals in the system. The
BREQ[1:0]# signals are interconnected in a rotating manner to individual processor pins.
Table A-1 gives the rotating interconnect between the processor and bus signals.
Table A-1. BR0#(I/O), BR1#, BR2#, BR3# Signals Rotating Interconnect
Bus Signal
BREQ0#
BREQ1#
During power-up configuration, the central agent must assert the BR0# bus signal. All
symmetric agents sample their BR[1:0]# pins on active-to-inactive transition of RESET#.
The pin on which the agent samples an active level determines its agent ID. All agents then
configure their pins to match the appropriate bus signal protocol, as shown in Table A-2.
Pin Sampled Active in RESET#
BR0#
BR1#
A-4
Agent 0 Pins
BR0#
BR1#
Table A-2. BR[3:0]# Signal Agent IDs
Agent 1 Pins
BR1#
BR0#
Agent ID
0
1
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