Table of Contents
Advertisement
SIGNALS REFERENCE
A.1.3.
ADS# (I/O)
The ADS# (Address Strobe) signal is asserted to indicate the validity of the transaction
address on the A[35:3]# pins. All bus agents observe the ADS# activation to begin parity
checking, protocol checking, address decode, internal snoop, or deferred reply ID match
operations associated with the new transaction. This signal must connect the appropriate pins
on all Pentium II processor system bus agents.
A.1.4.
AERR# (I/O)
The AERR# (Address Parity Error) signal is observed and driven by all Pentium II processor
system bus agents, and if used, must connect the appropriate pins on all Pentium II processor
system bus agents. AERR# observation is optionally enabled during power-on configuration;
if enabled, a valid assertion of AERR# aborts the current transaction.
If AERR# observation is disabled during power-on configuration, a central agent may handle
an assertion of AERR# as appropriate to the Machine Check Architecture (MCA) of the
system.
A.1.5.
AP[1:0]# (I/O)
The AP[1:0]# (Address Parity) signals are driven by the request initiator along with ADS#,
A[35:3]#, REQ[4:0]#, and RP#. AP1# covers A[35:24]#, and AP0# covers A[23:3]#. A
correct parity signal is high if an even number of covered signals are low and low if an odd
number of covered signals are low. This allows parity to be high when all the covered signals
are high. AP[1:0]# should connect the appropriate pins of all Pentium II processor system bus
agents.
A.1.6.
BCLK (I)
The BCLK (Bus Clock) signal determines the bus frequency. All Pentium II processor system
bus agents must receive this signal to drive their outputs and latch their inputs on the BCLK
rising edge.
All external timing parameters are specified with respect to the BCLK signal.
A.1.7.
BERR# (I/O)
The BERR# (Bus Error) signal is asserted to indicate an unrecoverable error without a bus
protocol violation. It may be driven by all Pentium II processor system bus agents, and must
connect the appropriate pins of all such agents, if used. However, Pentium II processors do
not observe assertions of the BERR# signal.
A-2
Advertisement
Table of Contents
