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Signals driven on the Pentium II processor system bus should meet signal quality
specifications to ensure that the components read data properly and that incoming signals do
not affect the long term reliability of the component. All wave terms described below are
simulated at the contact to the processor edge fingers.
9.1.
SYSTEM BUS CLOCK (BCLK) SIGNAL QUALITY
SPECIFICATIONS
Table 9-1 describes the signal quality for the system bus clock (BCLK) signal. Figure 9-1
describes the signal quality waveform for the system bus clock.
T#
Parameter
V1:
BCLK V
IL
V2:
BCLK V
IH
V3:
V
Absolute Voltage
IN
Range
V4:
Rising Edge Ringback
V5:
Falling Edge Ringback
V6:
Tline Ledge Voltage
V7:
Tline Ledge Oscillation
NOTES:
1.
The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling)
absolute voltage the BCLK signal can dip back to after passing the V
limits.
2.
The BCLK at the processor edge fingers may have a dip or ledge midway on the rising or falling edge.
The midpoint voltage level of this ledge must be within the range specified.
3.
The ledge (V7) is allowed to have peak-to-peak oscillation as specified.
SIGNAL QUALITY SPECIFICATIONS
Table 9-1. BCLK Signal Quality Specifications
Min
Nom
1.8
–0.5
2.0
1.0
CHAPTER 9
Max
Unit
Figure
0.7
V
9-1
V
9-1
3.3
V
9-1
V
9-1
0.5
V
9-1
1.7
V
9-1
0.2
V
9-1
(rising) or V
IH
Notes
Overshoot,
Undershoot
(1)
Absolute Value
Absolute Value
(1)
At Ledge
Midpoint
(2)
Peak-to-Peak
(3)
(falling) voltage
IL
9-1
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