National Instruments VXI-MXI-Express Series User Manual page 77

bus master
byte order
C
C
CLK10
Commander
configuration registers
D
Data Transfer Bus
DMA
DRAM
© National Instruments
A device that is capable of requesting the Data Transfer Bus (DTB) for the
purpose of accessing a slave device.
How bytes are arranged within a word or how words are arranged within
a longword. Motorola ordering stores the most significant byte (MSB)
or word first, followed by the least significant byte (LSB) or word. Intel
ordering stores the LSB or word first, followed by the MSB or word.
Celsius
A 10 MHz, ±100 ppm, individually buffered (to each module slot),
differential ECL system clock that is sourced from Slot 0 of a VXIbus
mainframe and distributed to Slots 1 through 12 on P2. It is distributed to
each slot as a single-source, single-destination signal with a matched delay
of under 8 ns.
A message-based device that is also a bus master and can control one or
more Servants.
A set of registers through which the system can identify a module
device type, model, manufacturer, address space, and memory requirements.
To support automatic system and memory configuration, the VXI
specification requires that all VXIbus devices have a set of such registers.
DTB; one of four buses on the VMEbus backplane. The DTB is used by a
bus master to transfer binary data between itself and a slave device.
Direct Memory Access—a method by which data is transferred between
devices and internal memory without intervention of the central processing
unit. DMA is the fastest method of transferring data to/from computer
memory.
Dynamic RAM (Random Access Memory)—storage that the computer
must refresh at frequent intervals.
Glossary-3 VXI-MXI-Express Series User Manual
Glossary