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204pin Unbuffered SODIMM
based on 4Gb A-die
78FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
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ⓒ 2010 Samsung Electronics Co., Ltd. All rights reserved.
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Rev. 1.0, Jul. 2010
M471B1G73AH0
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Summary of Contents for Samsung M471B1G73AH0
- Page 1 Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.
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Page 2: Revision History
Rev. 1.0 datasheet DDR3 SDRAM Unbuffered SODIMM Revision History Revision No. History Draft Date Remark Editor - First Release Jul. 2010 S.H.Kim - 2 -... -
Page 3: Table Of Contents
16. Timing Parameters by Speed Grade ... 26 16.1 Jitter Notes ... 29 16.2 Timing Parameter Notes... 30 17. Physical Dimensions : ... 31 17.1 512Mx8 based 1Gx64 Module (2 Ranks) - M471B1G73AH0... 31 datasheet - 3 - Rev. 1.0... -
Page 4: Ddr3 Unbuffered Sodimm Ordering Information
Unbuffered SODIMM 1. DDR3 Unbuffered SODIMM Ordering Information Part Number M471B1G73AH0-CF8/H9 NOTE : 1. "##" - F8/H9 2. F8 - 1066Mbps 7-7-7 & H9 - 1333Mbps 9-9-9 - DDR3-1333(9-9-9) is backward compatible to DDR3-1066(7-7-7) 2. Key Features DDR3-800 Speed 6-6-6... -
Page 5: X64 Dimm Pin Configurations (Front Side/Back Side)
3. This address might be connected to NC balls of the DRAMs (depending on density); either way they will be connected to the termination resistor. SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. datasheet... -
Page 6: Pin Description
Unbuffered SODIMM 5. Pin Description Pin Name Description CK0, CK1 Clock Inputs, positive line CK0, CK1 Clock Inputs, negative line CKE0, CKE1 Clock Enables Row Address Strobe Column Address Strobe Write Enable S0, S1 Chip Selects A0-A9, A11, Address Inputs A13-A15 A10/AP Address Input/Autoprecharge... -
Page 7: Input/Output Functional Description
Unbuffered SODIMM 6. Input/Output Functional Description Symbol Type The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and CK0-CK1 Input falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read opera- CK0-CK1 tions is synchronized to the input clock. -
Page 8: Function Block Diagram
Unbuffered SODIMM 7. Function Block Diagram: 7.1 8GB, 1Gx64 Module (Populated as 2 ranks of x8 DDR3 SDRAMs) Ω DQS3 ± DQS3 DQ[0:7] DQ[24:31] Ω DQS1 ± DQS1 DQ[0:7] DQ[8:15] Ω DQS0 ± DQS0 DQ[0:7] DQ[0:7] Ω DQS2 ± DQS2 DQ[16:23] DQ[0:7] (SPD) -
Page 9: Absolute Maximum Ratings
Unbuffered SODIMM 8. Absolute Maximum Ratings 8.1 Absolute Maximum DC Ratings Symbol Parameter Voltage on V pin relative to V Voltage on V pin relative to V Voltage on any pin relative to V Storage Temperature NOTE : 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. -
Page 10: Ac & Dc Input Measurement Levels
Unbuffered SODIMM 10. AC & DC Input Measurement Levels 10.1 AC & DC Logic Input Levels for Single-ended Signals [ Table 1 ] Single-ended AC & DC input levels for Command and Address Symbol Parameter (DC100) DC input logic high IH.CA (DC100) DC input logic low IL.CA... -
Page 11: Vref Tolerances
Unbuffered SODIMM 10.2 V Tolerances. The dc-tolerance limits and ac-noise limits for the reference voltages V (t) as a function of time. (V stands for V (DC) is the linear average of V (t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements of V thermore V (t) may temporarily deviate from V voltage... -
Page 12: Ac And Dc Logic Input Levels For Differential Signals
Unbuffered SODIMM 10.3 AC and DC Logic Input Levels for Differential Signals 10.3.1 Differential Signals Definition .DIFF.AC.MIN .DIFF.AC.MAX Figure 2. Definition of differential ac-swing and "time above ac level" tDVAC 10.3.2 Differential Swing Requirement for Clock (CK-CK) and Strobe (DQS-DQS) Symbol Parameter differential input high... -
Page 13: Single-Ended Requirements For Differential Signals
Unbuffered SODIMM 10.3.3 Single-ended Requirements for Differential Signals Each individual component of a differential signal (CK, DQS, CK, DQS) has also to comply with certain requirements for single-ended signals. CK and CK have to approximately reach V half-cycle. DQS, DQS have to reach V min / V max (approximately the ac-levels ( V ing a valid transition. -
Page 14: Differential Input Cross Point Voltage
Unbuffered SODIMM 10.3.4 Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage V cross point of true and complement signal to the mid level between of V [ Table 5 ] Cross point voltage for differential input signals (CK, DQS) Symbol... -
Page 15: Ac & Dc Output Measurement Levels
Unbuffered SODIMM 11. AC & DC Output Measurement Levels 11.1 Single Ended AC and DC Output Levels [ Table 7 ] Single Ended AC and DC output levels Symbol Parameter (DC) DC output high measurement level (for IV curve linearity) (DC) DC output mid measurement level (for IV curve linearity) (DC) -
Page 16: Differential Output Slew Rate
Unbuffered SODIMM 11.4 Differential Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V (AC) for differential signals as shown in below. diff [ Table 11 ] Differential Output slew rate definition Description Differential output slew rate for rising edge Differential output slew rate for falling edge... -
Page 17: Dimm Idd Specification Definition
Unbuffered SODIMM 12. DIMM IDD specification definition Symbol Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, CL: Refer to Component Datasheet for detail pattern ; BL: 8 IDD0 Command, Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... - Page 18 Rev. 1.0 datasheet DDR3 SDRAM Unbuffered SODIMM NOTE : 1) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B 2) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B 3) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit 4) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature 5) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range...
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Page 19: Idd Spec Table
Unbuffered SODIMM 13. IDD SPEC Table M471B1G73AH0 : 8GB (1Gx64) Module Symbol (DDR3-1066@CL=7) IDD0 IDD1 IDD2P0(slow exit) IDD2P1(fast exit) IDD2N IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5B IDD6 IDD7 IDD8 NOTE : 1. DIMM IDD SPEC is calculated with considering de-actived rank(IDLE) is IDD2N. -
Page 20: Input/Output Capacitance
14. Input/Output Capacitance 14.1 2Rx8 2GB SODIMM Parameter Input/output capacitance (DQ, DM, DQS, DQS, TDQS, TDQS) Input capacitance (CK and CK) Input capacitance (All other input-only pins) datasheet M471B1G73AH0 Symbol DDR3-1066 - 20 - Rev. 1.0 DDR3 SDRAM DDR3-1333 Units... -
Page 21: Electrical Characteristics And Ac Timing
Unbuffered SODIMM 15. Electrical Characteristics and AC timing (0 °C<T ≤95 °C, V = 1.5V ± 0.075V; V CASE 15.1 Refresh Parameters by Device Density Parameter All Bank Refresh to active/refresh cmd time Average periodic refresh interval NOTE : 1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in this material. - Page 22 Unbuffered SODIMM [ Table 14 ] DDR3-1066 Speed Bins Speed CL-nRCD-nRP Parameter Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CWL = 5 CL = 5 CWL = 6...
- Page 23 Unbuffered SODIMM [ Table 15 ] DDR3-1333 Speed Bins Speed CL-nRCD-nRP Parameter Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CWL = 5 CL = 5 CWL = 6,7...
- Page 24 Unbuffered SODIMM [ Table 16 ] DDR3-1600 Speed Bins Speed CL-nRCD-nRP Parameter Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CWL = 5 CL = 5 CWL = 6,7,8...
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Page 25: Speed Bin Table Notes
Unbuffered SODIMM 15.3.1 Speed Bin Table Notes Absolute Specification (T = 1.5V +/- 0.075 V); OPER NOTE : 1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting. -
Page 26: Timing Parameters By Speed Grade
Unbuffered SODIMM 16. Timing Parameters by Speed Grade [ Table 17 ] Timing Parameters by Speed Bin Speed Parameter Clock Timing tCK(DLL_OF Minimum Clock Cycle Time (DLL off mode) Average Clock Period Clock Period Average high pulse width Average low pulse width Clock Period Jitter Clock Period Jitter during DLL locking period tJIT(per, lck) - Page 27 Unbuffered SODIMM [ Table 17 ] Timing Parameters by Speed Bin (Cont.) Speed Parameter Command and Address Timing DLL locking time internal READ Command to PRECHARGE Command delay Delay from start of internal write transaction to internal read command WRITE recovery time Mode Register Set command cycle time Mode Register Set command update delay CAS# to CAS# command delay...
- Page 28 Unbuffered SODIMM [ Table 17 ] Timing Parameters by Speed Bin (Cont.) Speed Parameter Power Down Timing Exit Power Down with DLL on to any valid com- mand;Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL Exit Precharge Power Down with DLL frozen to com- mands requiring a locked DLL CKE minimum pulse width...
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Page 29: Jitter Notes
Unbuffered SODIMM 16.1 Jitter Notes Specific Note a Unit ’tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ’nCK’ represents one clock cycle of the input clock, counting the actual clock edges.ex) tMRD = 4 [nCK] means; if one Mode Register Set command is registered at Tm, another Mode Register Set command may be registered at Tm+4, even if (Tm+4 - Tm) is 4 x tCK(avg) + tERR(4per),min. -
Page 30: Timing Parameter Notes
Unbuffered SODIMM 16.2 Timing Parameter Notes 1. Actual value dependant upon measurement level definitions which are TBD. 2. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands. 3. The max values are system dependent. 4. WR as programmed in mode register 5. -
Page 31: Physical Dimensions
Unbuffered SODIMM 17. Physical Dimensions : 17.1 512Mx8 based 1Gx64 Module (2 Ranks) - M471B1G73AH0 24.80 1.80 0.10 (OPTIONAL HOLES) 1.65 1.00 ± 0.10 Detail A The used device is 512M x8 DDR3 SDRAM, FBGA. DDR3 SDRAM Part NO : K4B4G0846A - HC** * NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.