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Unbuffered DIMM
11.3.3 Single-ended Requirements for Differential Signals
Each individual component of a differential signal (CK, DQS, CK, DQS) has also to comply with certain requirements for single-ended signals.
CK and CK have to approximately reach V
half-cycle.
DQS, DQS have to reach V
min / V
SEH
ing a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ's might be different per speed-bin etc. E.g. if V
signals, then these ac-levels apply also for the single-ended signals CK and CK .
V
DD
V
/2 or V
DD
V
V
SS
Note that while ADD/CMD and DQ signal requirements are with respect to V
with respect to V
/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-
DD
ended components of differential signals the requirement to reach V
mode characteristics of these signals.
[ Table 6 ] Single ended levels for CK, DQS, CK, DQS
Symbol
Single-ended high-level for strobes
V
SEH
Single-ended high-level for CK, CK
Single-ended low-level for strobes
V
SEL
Single-ended low-level for CK, CK
NOTE :
1. For CK, CK use V
/V
(AC) of ADD/CMD; for strobes (DQS, DQS) use V
IH
IL
2. V
(AC)/V
(AC) for DQs is based on V
IH
IL
reduced level applies also here
3. These values are not defined, however the single-ended signals CK, CK, DQS, DQS need to be within the respective limits (V
nals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot Specification"
datasheet
min / V
max (approximately equal to the ac-levels ( V
SEH
SEL
max (approximately the ac-levels ( V
SEL
or V
DDQ
V
min
SEH
/2
DDQ
max
SEL
or V
SSQ
Figure 4. Single-ended requirement for differential signals
Parameter
; V
(AC)/V
(AC) for ADD/CMD is based on V
REFDQ
IH
IL
(AC) / V
(AC) ) for DQ signals) in every half-cycle proceeding and follow-
IH
IL
V
SEH
, the single-ended components of differential signals have a requirement
REF
max, V
min has no bearing on timing, but adds a restriction on the common
SEL
SEH
DDR3-800/1066/1333/1600
Min
(V
/2)+0.175
DD
(V
/2)+0.175
DD
NOTE 3
NOTE 3
/V
(AC) of DQs.
IH
IL
; if a reduced ac-high or ac-low level is used for a signal group, then the
REFCA
- 17 -
DDR3L SDRAM
(AC) / V
(AC) ) for ADD/CMD signals) in every
IH
IL
150(AC)/V
150(AC) is used for ADD/CMD
IH
IL
CK or DQS
V
SEL
time
Max
NOTE 3
NOTE 3
(V
/2)-0.175
DD
(V
/2)-0.175
DD
(DC) max, V
(DC)min) for single-ended sig-
IH
IL
Rev. 1.0
Unit
NOTE
V
1, 2
V
1, 2
V
1, 2
V
1, 2
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