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Unbuffered DIMM
13. IDD specification definition
Symbol
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: Refer to Component Datasheet for detail pattern ; BL: 8
IDD0
Command, Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active at a time:
0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers
tern
Operating One Bank Active-Read-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: Refer to Component Datasheet for detail pattern ; BL: 8
IDD1
and PRE; Command, Address, Bank Address Inputs, Data IO: partially toggling ; DM:stable at 0; Bank Activity: Cycling with one bank active at a time:
0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers
tern
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
IDD2N
Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode
2)
Registers
; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
IDD2P0
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exit
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
IDD2P1
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exit
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
IDD2Q
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
ODT Signal: stable at 0
Active Standby Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
IDD3N
Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode
2)
Registers
; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
IDD3P
Address Inputs: stable at 0; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers
Signal: stable at 0
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
IDD4R
Bank Address Inputs: partially toggling ; Data IO: seamless read data burst with different data between one burst and the next one ; DM:stable at 0; Bank
Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers
at 0; Pattern Details: Refer to Component Datasheet for detail pattern
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
IDD4W
Bank Address Inputs: partially toggling ; Data IO: seamless write data burst with different data between one burst and the next one ; DM: stable at 0; Bank
Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers
at HIGH; Pattern Details: Refer to Component Datasheet for detail pattern
Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: Refer to Component Datasheet for detail pattern ; BL: 8
IDD5B
Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC ; Output Buffer and
RTT: Enabled in Mode Registers
Self Refresh Current: Normal Temperature Range
TCASE: 0 - 85°C; Auto Self-Refresh (ASR): Disabled
IDD6
LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 8
Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers
Self-Refresh Current: Extended Temperature Range (optional)
TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Disabled
IDD6ET
LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 8
Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: Refer to Component Datasheet for detail pattern ; BL: 8
IDD7
between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling ; Data IO: read data bursts with different data between one burst and
the next one ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing ; Output Buffer and RTT:
Enabled in Mode Registers
RESET Low Current
IDD8
RESET : Low; External clock : off; CK and CK : LOW; CKE : FLOATING ; CS, Command, Address, Bank Address, Data IO : FLOATING ; ODT Signal :
FLOATING
datasheet
2)
; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
4)
; Self-Refresh Temperature Range (SRT): Normal
4)
; Self-Refresh Temperature Range (SRT): Extended
2)
; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
Description
2)
; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pat-
2)
; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pat-
1)
; AL: 0; CS: stable at 1; Command, Address, Bank
1)
; AL: 0; CS: stable at 1; Command, Address, Bank
3)
1)
; AL: 0; CS: stable at 1; Command, Address, Bank
3)
1)
; AL: 0; CS: stable at 1; Command, Address, Bank
1)
; AL: 0; CS: stable at 1; Command, Address, Bank
1)
; AL: 0; CS: stable at 1; Command, Address, Bank
1)
; AL: 0; CS: High between RD; Command, Address,
1)
; AL: 0; CS: High between WR; Command, Address,
1)
; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0;
2)
; ODT Signal: FLOATING
6)
1)
; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0;
- 22 -
DDR3L SDRAM
1)
; AL: 0; CS: High between ACT and PRE;
1)
; AL: 0; CS: High between ACT, RD
2)
; ODT Signal: stable
2)
; ODT Signal: stable
1)
; AL: 0; CS: High between REF; Command,
5)
; CKE: Low; External clock: Off; CK and CK:
5)
; CKE: Low; External clock: Off; CK and CK:
2)
; ODT Signal: FLOATING
1)
; AL: CL-1; CS: High
Rev. 1.0
2)
;
2)
;
2)
;
2)
; ODT
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