Samsung M391B5273DH0 Hardware User Manual page 31

Unbuffered DIMM
[ Table 21 ] Timing Parameters by Speed Bin (Cont.)
Speed
Parameter
Data Strobe Timing
DQS, DQS differential READ Preamble
DQS, DQS differential READ Postamble
DQS, DQS differential output high time
DQS, DQS differential output low time
DQS, DQS differential WRITE Preamble
DQS, DQS differential WRITE Postamble
DQS, DQS rising edge output access time from rising
CK, CK
DQS, DQS low-impedance time (Referenced from RL-
1)
DQS, DQS high-impedance time (Referenced from
RL+BL/2)
DQS, DQS differential input low pulse width
DQS, DQS differential input high pulse width
DQS, DQS rising edge to CK, CK rising edge
DQS,DQS falling edge setup time to CK, CK rising edge
DQS,DQS falling edge hold time to CK, CK rising edge
Command and Address Timing
DLL locking time
internal READ Command to PRECHARGE Command
delay
Delay from start of internal write transaction to internal
read command
WRITE recovery time
Mode Register Set command cycle time
Mode Register Set command update delay
CAS# to CAS# command delay
Auto precharge write recovery + precharge time
Multi-Purpose Register Recovery Time
ACTIVE to PRECHARGE command period
ACTIVE to ACTIVE command period for 1KB page size
ACTIVE to ACTIVE command period for 2KB page size
Four activate window for 1KB page size
Four activate window for 2KB page size
Command and Address setup time to CK, CK refer-
enced to V (AC) / V (AC) levels
IH IL
Command and Address hold time from CK, CK refer-
enced to V (AC) / V (AC) levels
IH IL
Command and Address setup time to CK, CK refer-
enced to V (AC) / V (AC) levels
IH IL
Control & Address Input pulse width for each input
Calibration Timing
Power-up and RESET calibration time
Normal operation Full calibration time
Normal operation short calibration time
datasheet
DDR3-800
Symbol MIN MAX
tRPRE 0.9 Note 19
tRPST 0.3 Note 11
tQSH 0.38 -
tQSL 0.38 -
tWPRE 0.9 -
tWPST 0.3 -
tDQSCK -400 400
tLZ(DQS) -800 400
tHZ(DQS) - 400
tDQSL 0.45 0.55
tDQSH 0.45 0.55
tDQSS -0.25 0.25
tDSS 0.2 -
tDSH 0.2 -
tDLLK 512 -
max
tRTP -
(4nCK,7.5ns) (4nCK,7.5ns)
max
tWTR -
(4nCK,7.5ns) (4nCK,7.5ns)
tWR 15 -
tMRD 4 -
max
tMOD -
(12nCK,15ns) (12nCK,15ns)
tCCD 4 -
tDAL(min)
tMPRR 1 -
tRAS See "Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin"
max
tRRD -
(4nCK,10ns) (4nCK,7.5ns)
max
tRRD -
(4nCK,10ns) (4nCK,10ns)
tFAW 40 -
tFAW 50 -
tIS(base)
-
215
AC160
tIS(base)
-
200
AC175
tIH(base)
-
285
DC90
tIH(base)
275
DC100
tIS(base)
-
365
AC135
tIS(base)
-
350
AC150
-
tIPW 900
tZQinitI 512 -
tZQoper 256 -
tZQCS 64 -
DDR3-1066 DDR3-1333
MIN MAX MIN
0.9 Note 19 0.9 Note 19
0.3 Note 11 0.3 Note 11
0.38 - 0.4
0.38 - 0.4
0.9 - 0.9
0.3 - 0.3
-300 300 -255
-600 300 -500
- 300 -
0.45 0.55 0.45
0.45 0.55 0.45
-0.25 0.25 -0.25
0.2 - 0.2
0.2 - 0.2
512 - 512
max max
-
(4nCK,7.5ns)
max max
-
(4nCK,7.5ns)
15 - 15
4 - 4
max max
-
(12nCK,15ns)
4 - 4
WR + roundup (tRP / tCK(AVG))
1 - 1
max max
-
(4nCK,6ns)
max max
-
(4nCK,7.5ns)
37.5 - 30
50 - 45
1.35V
-
140 80
1.5V
-
125 65
1.35V
-
210 150
1.5V
200 140
1.35V
-
290 205
1.5V
-
275 190
-
780 620
512 - 512
256 - 256
64 - 64
- 31 -
DDR3L SDRAM
DDR3-1600
Units
MAX MIN MAX
0.9 Note 19 tCK
0.3 Note 11 tCK
- 0.4 - tCK(avg)
- 0.4 - tCK(avg)
- 0.9 - tCK
- 0.3 - tCK
255 -225 225 ps
250 -450 225 ps
250 - 225 ps
0.55 0.45 0.55 tCK
0.55 0.45 0.55 tCK
0.25 -0.27 0.27 tCK(avg)
- 0.18 - tCK(avg)
- 0.18 - tCK(avg)
- 512 - nCK
max
- -
(4nCK,7.5ns)
max
- -
(4nCK,7.5ns)
- 15 - ns
- 4 - nCK
max
- -
(12nCK,15ns)
- 4 - nCK
nCK
- 1 - nCK
ns
max
- -
(4nCK,6ns)
max
- -
(4nCK,7.5ns)
- 30 - ns
- 40 - ns
- 60 - ps
- 45 - ps
- 130 - ps
120 - ps
- 185 - ps
- 170 - ps
- 560 - ps
- 512 - nCK
- 256 - nCK
- 64 - nCK
Rev. 1.0
NOTE
13, 19, g
11, 13, b
13, g
13, g
13,f
13,14,f
12,13,14
29, 31
30, 31
c
c, 32
c, 32
e
e,18
e
22
e
e
e
e
e
b,16
b,16
b,16
b,16
b,16,27
b,16,27
28
23