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UPD784217AGF139 (IC500) : MD micon
1. Pin layout
100
1
25
26
2. Block diagram
INTP2/NMI
PROGRAMMABLE
INTP0.INTP1.
INTERRUPT
INTP3-INTP6
CONTROLLER
TI00
TIMER/EVENT
TI01
COUNTER
(16BITS)
TO0
TIMER/EVENT
TI1
COUNTER1
TO1
(8BITS)
TIMER/EVENT
TI2
COUNTER2
TO2
(8BITS)
TIMER/EVENT
TI5/TO5
COUNTER5
(8BITS)
TIMER/EVENT
TI6/TO6
COUNTER6
(8BITS)
TIMER/EVENT
TI7/TO7
COUNTER7
(8BITS)
TIMER/EVENT
TI8/TO8
COUNTER8
(8BITS)
WATCH TIMER
WATCHDOG TIMER
RTP0-RTP7
REAL-TIME
OUTPUT PORT
ANO0
ANO1
D/A
AV
REF1
CONVERTER
AV
SS
ANI0-ANI7
A/D
AV
REF0
AV
D0
CONVERTER
AV
SS
P03/INTP3
CLOCK OUTPUT
PCL
CONTROL
BUZZER OUTPUT
BUZ
76
75
51
50
78K/1V
ROM
CPU CORE
128K BITS
RAM
8192BITS
UX-F70MD/UX-F72MD
RxD1/SI1
UART/IOE1
TxD1/SO1
BAUD-RATE
ASCK1/SCK1
GENERATOR
RxD2/SI2
UART/IOE2
TxD2/SO2
BAUD-RATE
ASCK2/SCK2
GENERATOR
CLOCKED
SI0
SO0
SERIAL
INTERFACE
SCK0
AD0-AD7
A0-A7
A8-A15
BUS I/F
A16-A19
RD
WR
WAIT
ASTB
PORT0
P00-P06
PORT1
P10-P17
PORT2
P20-P27
PORT3
P30-P37
PORT4
P40-P47
PORT5
P50-P57
PORT6
P60-P67
PORT7
P70-P72
PORT8
P80-P87
PORT9
P90-P95
PORT10
P100-P103
PORT12
P120-P127
PORT13
P130.P131
RESET
X1
SYSTEM CONTROL
X2
XT1
XT2
V
DD
V
SS
TEST
1-47
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