Sdram Write; Sdram Three-Word Write Timing Diagram - Texas Instruments TMS320C6000 DSP Reference Manual

SDRAM Interface
2.4.8

SDRAM Write

Figure 2−10. SDRAM Three-Word Write Timing Diagram
2-16 TMS320C620x/C670x EMIF
All SDRAM writes have a burst length of one on the C620x/C670x EMIF. The
bank is activated with the row address during the ACTV command. There is no
latency on writes, so data is output on the same cycle as the column address.
Writes to particular bytes are disabled using the appropriate DQM inputs; this
feature allows for byte and halfword writes. Figure 2−10 shows the timing for a
three-word write on the EMIF. Since the default write-burst length is one word, a
new write command is issued each cycle to perform the three-word burst. Follow-
ing the final write command, the EMIF inserts an idle cycle to meet SDRAM
timing requirements. The bank is then deactivated with a DCAB command, and
the memory interface can begin a new page access. If no new access is pend-
ing, the DCAB command is not performed until the page information becomes
invalid (see section 2.4.2). The values on EA[15:13] (if SDWID = 1) or
EA[14:13] (if SDWID = 0) during column accesses and the DCAB command
are the values latched during the ACTV command.
If a page boundary is crossed during the course of an access, the EMIF
performs a DCAB command and starts a new row access. If a write burst
crosses a page boundary, the CAS and WE signals stay active for one
additional cycle before the DCAB command. The BE signals are inactive high
during this additional cycle to prevent the EMIF from incorrectly writing an extra
word.
†
Clock
CEn
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
SDRAS
SDCAS
SDWE
†
Clock = SDCLK for C6201/C6701 DSP.
= CLKOUT2 for all other C620x/C670x DSP, except C6201/C6701 DSP.
Write Write
BE1 BE2 BE3
CA1 CA2 CA3
D1 D2
D3
Write
SPRU266A