Address Shift - Texas Instruments TMS320C6000 DSP Reference Manual

3.4.2

Address Shift

SPRU266A
The same EMIF pins determine the row and column address, thus the
C621x/C671x EMIF interface appropriately shifts the address in row and
column address selection. Table 3−4 describes the addressing for a 8-, 16-,
and 32-bit-wide SDRAM interface. The address presented on the pins are
shifted for 8-bit and 16-bit interfaces.
The following factors apply to the address shifting process:
The address shift is controlled completely by the column size field
-
(SDCSZ) and is unaffected by the bank and row size fields. The bank and
row size are used internally to determine whether a page is opened.
The address bits corresponding to the bank select bits are latched inter-
-
nally by the SDRAM controller during a RAS cycle. The bank select bits
are:
EA[13 + n:13] for SDRSZ = 00b (11 row pins)
J
EA[14 + n:14] for SDRSZ = 01b (12 row pins)
J
EA[15 + n:15] for SDRSZ = 11b (13 row pins)
J
where n = 0, when SDBSZ = 0; and n = 1, when SDBSZ = 1. This
ensures that the SDRAM bank select inputs are correct during READ
and WRT commands. Thus, the EMIF maintains these values as
shown in both row and column addresses.
EA12 is connected directly to A10 signal, instead of using a dedicated
-
precharge pin SDA10.
SDRAM Interface
TMS320C621x/C671x EMIF 3-13