Emif Ce Space Control Register (Cectl) - Texas Instruments TMS320C6000 DSP Reference Manual

Figure 4−37. EMIF CE Space Control Register (CECTL)
31 28 27
WRSETUP
R/W-1111
15 14 13
TA
R/W-11
Legend: R/W = Read/Write; -n = value after reset
Table 4−17. EMIF CE Space Control Register (CECTL) Field Descriptions
Bit †
field
31−28 WRSETUP
27−22 WRSTRB
21−20 WRHLD
19−16 RDSETUP
15−14 TA
13−8 RDSTRB
†
For CSL implementation, use the notation EMIFA_CECTL_field_symval or EMIFB_CECTL_field_symval.
‡
Clock cycles are in terms of ECLKOUT1 for C64x DSP.
§
32-bit and 64-bit interfaces (MTYPE=0010b, 0011b, 0100b, 1100b, 1101b, 1110b) do not apply to C64x EMIFB.
SPRU266A
WRSTRB
R/W-11 1111
RDSTRB
R/W-11 1111
† Value Description
symval
OF(value) 0−Fh Write setup width. Number of clock cycles
address (EA), chip enable (CE), and byte enables (BE)
before write strobe falls. For asynchronous read accesses,
this is also the setup time of AOE before ARE falls.
OF(value) 0−3Fh Write strobe width. The width of write strobe (AWE) in clock
cycles.
OF(value) 0−3h Write hold width. Number of clock cycles
and byte strobes (BE) are held after write strobe rises. For
asynchronous read accesses, this is also the hold time of
AOE after ARE rising.
OF(value) 0−Fh Read setup width. Number of clock cycles
address (EA), chip enable (CE), and byte enables (BE)
before read strobe falls. For asynchronous read accesses,
this is also the setup time of AOE before ARE falls.
OF(value) 0−3h Minimum Turn-Around time. Turn-around time controls the
minimum number of ECLKOUT cycles
followed by a write (same or different CE spaces), or between
reads from different CE spaces. Applies only to asynchronous
memory types.
OF(value) 0−3Fh Read strobe width. The width of read strobe (ARE) in clock
cycles.
22 21 20 19
WRHLD
R/W-11
8 7 4
MTYPE
R/W-0
‡
‡
EMIF Registers
RDSETUP
R/W-1111
3 2
WRHLDMSB RDHLD
R/W-0 R/W-011
‡
of setup time for
‡ that address (EA)
‡ of setup time for
‡ between a read
TMS320C64x EMIF
16
0
4-61