Texas Instruments TMS320C6000 DSP Reference Manual page 148

Peripheral Device Transfer (PDT)
4.6.1 PDT Write
4-38 TMS320C64x EMIF
A PDT write transfer refers to a transfer from a peripheral to memory, in which
the memory is physically written. To enable a PDT write transfer, set the PDTD
bit in the EDMA options field to 1. The assertion/deassertion of the PDT
address pins (PDTA and PDTDIR) and the PDT pin are timed according to the
destination memory clock. Since the destination memory is SDRAM,
ECLKOUT1 is used.
A PDT write transfer procedure is as follows:
1) The destination address is to a CE space set as SDRAM:
The PDT access bit (PDTA) and the PDT direction (PDTDIR) are used
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to give the system advance warning that a PDT transaction is pending.
The system may then activate bus switches or other external logic that
controls the actual PDT transfer.
If the access is to a closed page, then during the ACTV cycle, PDTA is
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low, and PDTDIR is low to indicate a write access.
If the access is to an open page previously accessed without a PDT
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operation, then the page will be closed and reopened, with the PDT
address pins asserted low during the ACTV cycle.
If the access is to an open page previously accessed with a PDT
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operation, then the access goes directly to the data phase.
2) Normal write control signals are generated to the appropriate CE space.
3) The write transaction proceeds as normal except:
EMIF data outputs remain in a high-impedance state. Therefore, the
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memory latches data from the peripheral device, instead of data from
the EMIF.
PDT is asserted low PDTWL cycles prior to the destination device
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latching the data. This implies that the peripheral must drive valid data
PDTWL cycles after PDT is active.
Figure 4−23 displays the timing diagram for a PDT write transaction.
SPRU266A