Emif Registers; Emif Global Control Register (Gblctl); Emif Sdram Control Register (Sdctl); Emif Registers For C620X/C670X Dsp - Texas Instruments TMS320C6000 DSP Reference Manual

2.8 EMIF Registers

Table 2−10. EMIF Registers for C620x/C670x DSP
Acronym Register Name
GBLCTL EMIF global control register
CECTL0 EMIF CE0 space control register
CECTL1 EMIF CE1 space control register
CECTL2 EMIF CE2 space control register
CECTL3 EMIF CE3 space control register
SDCTL EMIF SDRAM control register
SDTIM EMIF SDRAM refresh control register
2.8.1

EMIF Global Control Register (GBLCTL)

SPRU266A
Control of the EMIF and the memory interfaces it supports is maintained
through memory-mapped registers within the EMIF. Access to these registers
requires the EMIF clock. Table 2−10 lists the memory-mapped registers and
their memory addresses in the C620x/C670x DSP.
The EMIF global control register (GBLCTL) configures parameters common
to all the CE spaces. The GBLCTL is shown in Figure 2−14 and Figure 2−15
and described in Table 2−11.
In order to support as many common programming practices as possible
between the C620x/C670x devices, the SSCEN and SDCEN fields are used
to enable the memory interface clock, CLKOUT2. If SBSRAM is used in the
system, as specified by the MTYPE field in the CE space control register
(CECTL), SSCEN enables or disables CLKOUT2. If SDRAM is used, as speci-
fied by MTYPE, SDCEN enables or disables CLKOUT2.
Hex Byte Address
0180 0000h
0180 0008h
0180 0004h
0180 0010h
0180 0014h
0180 0018h
0180 001Ch
TMS320C620x/C670x EMIF
EMIF Registers
Section
2.8.1
2.8.2
2.8.2
2.8.2
2.8.2
2.8.3
2.8.4
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