Standard Synchronous Fifo Write Timing Diagram - Texas Instruments TMS320C6000 DSP Reference Manual

Programmable Synchronous Interface
4.5.3.2 Standard Synchronous FIFO Write
Figure 4−21. Standard Synchronous FIFO Write Timing Diagram
ECLKOUTn
CEn
†
BE[3:0]
†
EA[22:3]
†
ED[31:0]
SRE (RENEN = 1)
SOE or SOE3
SWE
†
For EMIFB: BE[1:0], EA[21:1], and ED[15:0] are used.
4.5.3.3 First Word Fall Through (FWFT) Synchronous FIFO Write
4-34 TMS320C64x EMIF
Figure 4−21 shows a six-word write to a standard synchronous FIFO. The
CESEC settings are:
SYNCWL = 00b; zero cycle write latency
-
RENEN = 1; SADS/SRE signal acts as SRE signal
-
Write
Write
BE1 BE2
A1 A2
WL = 0
D1 D2
The first word fall through (FWFT) synchronous FIFO write timing is identical
to the standard synchronous FIFO write timing, see section 4.5.3.2.
Write Write
BE3 BE4 BE5
A3 A4 A5
D3 D4 D5
Write
Write
BE6
A6
D6
SPRU266A