Standard Synchronous Fifo Read Timing Diagram (Ce3 Only) - Texas Instruments TMS320C6000 DSP Reference Manual

Figure 4−20. Standard Synchronous FIFO Read Timing Diagram (CE3 only)
ECLKOUTn
†
CE3 (CEEXT = 0)
†
CE3 (CEEXT = 1)
‡
BE[7:0]
‡
EA[all]
‡
ED[63:0]
SRE (RENEN = 1)
SOE
SOE3
SWE
†
CEEXT = 0 for glueless synchronous FIFO interface. CEEXT = 1 for interface with glue.
‡
Figure shows 64-bit interface. The MTYPE field selects the interface type to be 8-, 16-, 32-, or 64-bits wide.
For 32-bit interface, BE[3:0], EA[all], and ED[31:0] are used.
For 16-bit interface, BE[1:0], EA[all], and ED[15:0] are used.
SPRU266A
Read
Read
BE1 BE2 BE3
A1
A2 A3
RL = 1
D1 D2
Programmable Synchronous Interface
Read Read Read
BE4 BE5
A4 A5
D3 D4
TMS320C64x EMIF
Read
BE6
A6
D5 D6
4-33