Figure 33. C64X Sdram Read-Cas Latency 3; Sdram Write (Wrt) - Texas Instruments TMS320C6000 Application Report

SPRA433E
ECLKOUT1
CEx
BE[7:0] †
EA[22:14] †
EA[12:3] †
ED[63:0] †
EA13 †
SDRAS
SDCAS
SDWE
EA19
For EMIFB, BE[1:0], EA[20:12], EA[10:1], ED[15:0], and EA11, respectively, are used.
If a refresh cycle is pending, a DCAB cycle will be performed to deactivate the bank. If an
access to a different page of memory in the same bank of SDRAM is required (that is, a page
miss), a DEAC command will be issued following the last column access, followed by an ACTV
to open the correct page.
3.1.5

SDRAM Write (WRT)

For an SDRAM write, the selected bank is activated with the row address during the ACTV
command. In this example, three write commands are performed to three successive column
addresses in the same page.
3.1.5.1 C620x/C670x SDRAM Writes
All SDRAM writes have a burst length of 1 (see Figure 34). The bank is activated with the row
address during the ACTV command. There is no latency on writes, so data is output on the
same cycle as the column address. Byte and half-word writes are enabled via the appropriate
DQM inputs. Following the final write command, an idle cycle is inserted to meet SDRAM timing
requirements. If required, the bank is then deactivated with a DCAB command ,and the memory
interface can begin a new page access. If no new access is pending, or if an access is pending
to the same page, the DCAB command is not performed until the page information becomes
invalid.
46 TMS320C6000 EMIF-to-External SDRAM Interface
t RCD = 3 cycles
ACTV
Bank/Row
Row
Row Address
†
Figure 33. C64x SDRAM Read—CAS Latency 3
Cas Latency = 3 cycles
C64x Latches Data
Read
BE1 BE2 BE3
Bank
Column
D1 D2 D3 D4