Emif Sdram Timing Register (Sdtim) - Texas Instruments TMS320C6000 DSP Reference Manual

Table 4−19. EMIF SDRAM Control Register (SDCTL) Field Descriptions (Continued)
Bit †
field symval
11−1 Reserved −
0 SLFRFR
DISABLE
ENABLE
DISABLE
ENABLE
†
For CSL implementation, use the notation EMIFA_SDCTL_field_symval or EMIFB_SDCTL_field_symval.
‡
t refers to the EMIF clock period, which is equal to ECLKOUT1 period for C64x DSP.
cyc
§
TRCD specifies the number of ECLKOUT1 cycles between an ACTV command and a READ or WRT command (CAS). The
specified separation is maintained while driving write data one cycle earlier.
4.8.5

EMIF SDRAM Timing Register (SDTIM)

SPRU266A
† Value Description
0 Reserved. The reserved bit location is always read as 0. A value
written to this field has no effect.
Self-refresh mode, if SDRAM is used in the system:
0 Self-refresh mode is disabled.
1 Self-refresh mode is enabled.
If SDRAM is not used:
0 General-purpose output, SDCKE = 1.
1 General-purpose output, SDCKE = 0.
The SDRAM timing register (SDTIM) controls the refresh period in terms of
EMIF clock cycles. The SDTIM is shown in Figure 4−40 and described in
Table 4−20. Optionally, the PERIOD field can send an interrupt to the CPU.
Thus, this counter can be used as a general-purpose timer if SDRAM is not
used by the system. The CPU can read the counter (CNTR) field. When the
counter reaches 0, it is automatically reloaded with the period and SDINT
(synchronization event to EDMA and interrupt source to CPU) is asserted. See
sections 4.4.3 and 1.3.3 for more information on SDRAM refresh.
The XRFR field controls the number of refreshes performed when the refresh
counter reaches 0. Up to four refreshes can be performed when the refresh
counter expires. For example, since all banks must be deactivated to perform
a refresh, it might be desirable to perform two refreshes half as often.
The system considers all refresh requests as high priority. When it is time to
refresh, the refresh is performed immediately (though transfers in progress are
allowed to complete). All banks are deactivated before a refresh command is
issued. When the refresh command is complete, the banks are not restored
to their state before refresh.
The initial value for the CNTR field and the PERIOD field is 5DCh (1500 clock
cycles). With a 10-ns EMIF cycle time, there is a 15-µs time between refresh
operations. SDRAMs typically require 15.625 µs per refresh.
EMIF Registers
TMS320C64x EMIF 4-67