Asynchronous Writes - Texas Instruments TMS320C6000 DSP Reference Manual

1.5.3

Asynchronous Writes

SPRU266A
Figure 1−10 shows two back-to-back asynchronous write cycles with the
ARDY signal pulled high (always ready). The SETUP, STROBE, and HOLD
are programmed to 2, 3, and 1, respectively.
At the beginning of the setup period:
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CE becomes active.
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BE[3:0] becomes valid.
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EA becomes valid.
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ED becomes valid. For the C621x/C671x EMIF, see section 1.5.3.1
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for the exact cycle where ED becomes valid.
For the C620x/C670x EMIF, the first access has a setup period
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minimum value of 2. After the first access, setup has a minimum value
of 1.
At the beginning of a strobe period, AWE becomes active.
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At the beginning of a hold period, AWE becomes inactive.
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At the end of the hold period:
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ED goes into the high-impedance state only if another write access to
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the same CE space is not scheduled for the next cycle.
CE becomes inactive only if another read or write access to the same
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CE space is not pending.
For the C620x/C670x EMIF: If no write accesses are scheduled for the
-
next cycle and write hold is set to 1 or greater, then CE stays active for
3 cycles after the value of the programmed hold period. If write hold is
cleared to 0, then CE stays active for four more cycles. This does not affect
performance and merely reflects the EMIF's overhead.
For the C621x/C671x EMIF and C64x EMIF: The CEn signal goes high
-
immediately after the programmed hold period.
Asynchronous Interface
Overview 1-21