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TMS320TCI648x
Texas Instruments TMS320TCI648x DSP Timer Manuals
Manuals and User Guides for Texas Instruments TMS320TCI648x DSP Timer. We have
2
Texas Instruments TMS320TCI648x DSP Timer manuals available for free PDF download: User Manual
Texas Instruments TMS320TCI648x User Manual (256 pages)
Texas Instruments Serial RapidIO (SRIO) User's Guide
Brand:
Texas Instruments
| Category:
Network Card
| Size: 2.63 MB
Table of Contents
Table of Contents
3
Preface
14
Overview
16
General Rapidio System
16
Rapidio Architectural Hierarchy
17
Rapidio Interconnect Architecture
18
Rapidio Feature Support in SRIO
19
Serial Rapidio Device to Device Interface Diagrams
19
Standards
20
External Devices Requirements
20
TI Devices Supported by this Document
20
SRIO Functional Description
21
Overview
21
Registers Checked for Multicast Deviceid
21
SRIO Peripheral Block Diagram
22
Operation Sequence
23
1X/4X Rapidio Packet Data Stream (Streaming-Write Class)
24
Serial Rapidio Control Symbol Format
24
SRIO Pins
25
Packet Types
25
Functional Operation
26
Pin Description
26
SRIO Component Block Diagram
27
SERDES Macro Configuration Register 0 (SERDES_CFG0_CNTL)
28
SERDES Macro Configuration Register 0 (SERDES_CFG0_CNTL) Field Descriptions
29
Line Rate Versus PLL Output Clock Frequency
30
Effect of the RATE Bits
30
Frequency Range Versus MPY Value
30
SERDES Receive Channel Configuration Register N (Serdes_Cfgrxn_Cntl)
31
EQ Bits
33
Descriptions
33
SERDES Transmit Channel Configuration Register N (Serdes_Cfgtxn_Cntl)
33
DE Bits of Serdes_Cfgtxn_Cntl
34
SWING Bits of Serdes_Cfgtxn_Cntl
35
Load/Store Registers for Rapidio
36
440H-458H, LSU4 460H-478H)
36
LSU Control/Command Register Fields
36
LSU Status Register Fields
37
LSU Registers Timing
38
Example Burst NWRITE_R
39
Load/Store Module Data Flow Diagram
40
CPPI RX Scheme for Rapidio
44
Message Request Packet
45
Mailbox to Queue Mapping Register Pair
46
RX DMA State Head Descriptor Pointer (HDP) (Address Offset 600H-63Ch)
46
RX DMA State Completion Pointer (CP) (Address Offset 680H-6Bch)
46
RX Buffer Descriptor Fields
47
RX Buffer Descriptor Field Descriptions
47
RX CPPI Mode Explanation
49
CPPI Boundary Diagram
51
TX DMA State Head Descriptor Pointer (HDP) (Address Offset 500H-53Ch)
51
TX Buffer Descriptor Fields
52
TX DMA State Completion Pointer (CP) (Address Offset 58H-5Bch)
52
TX Buffer Descriptor Field Definitions
52
Weighted Round Robin Programming Registers (Address Offset 7E0H-7Ech)
56
RX Buffer Descriptors
62
TX Buffer Descriptors
63
Doorbell Operation
64
Flow Control Table Entry Registers (Address Offset 0900H-093Ch)
66
Transmit Source Flow Control Masks
67
Fields Within each Flow Mask
67
Flow Control Table Entry Register N (Flow_Cntln) Field Descriptions
67
Fields Within each Flow Mask
68
Configuration Bus Example
69
DMA Example
69
Reset Hierarchy
70
GBL_EN (Address 0030H)
71
GBL_EN_STAT (Address 0034H)
71
BLK0_EN (Address 0038H)
72
Global Enable and Global Enable Status Field Descriptions
72
BLK0_EN_STAT (Address 003Ch)
73
BLK1_EN (Address 0040H)
73
BLK1_EN_STAT (Address 0044H)
73
BLK8_EN (Address 0078H)
73
BLK8_EN_STAT (Address 007Ch)
73
Block Enable and Block Enable Status Field Descriptions
73
Peripheral Control Register (PCR) - Address Offset 0004H
74
Peripheral Control Register (PCR) Field Descriptions
74
Port Mode Register Settings
77
Bootload Operation
80
Packet Forwarding Register N for 16-Bit Device Ids (Pf_16B_Cntln) Offsets 0X0090, 0X0098, 0X00A0, 0X00A8
81
Packet Forwarding Register N for 16-Bit Device Ids (Pf_16B_Cntln)
81
Multicast Deviceid Operation
81
Packet Forwarding Register N for 16-Bit Deviceids (Pf_16B_Cntln) Field Descriptions
81
Packet Forwarding Register N for 8-Bit Device Ids (Pf_8B_Cntln) Offsets 0X0094, 0X009C, 0X00A4, 0X00Ac
82
Packet Forwarding Register N for 8-Bit Device Ids (Pf_8B_Cntln)
82
Packet Forwarding Register N for 8-Bit Deviceids (Pf_8B_Cntln) Field Descriptions
82
Logical/Transport Error Handling and Logging
83
Logical/Transport Layer Error Detect CSR (ERR_DET) Field Descriptions
83
Logical/Transport Layer Error Detect CSR (ERR_DET)
84
Logical/Transport Layer Error Detect CSR (ERR_DET) Field Descriptions
84
Interrupt Conditions
85
CPU Interrupts
85
General Description
85
Rapidio DOORBELL Packet for Interrupt Use
85
Interrupt Condition Status and Clear Registers
86
Doorbell 0 Interrupt Condition Status and Clear Registers
87
Doorbell 1 Interrupt Condition Status and Clear Registers
87
Interrupt Condition Status and Clear Bits
87
Doorbell 2 Interrupt Condition Status and Clear Registers
88
Doorbell 3 Interrupt Condition Status and Clear Registers
88
RX CPPI Interrupt Condition Status and Clear Registers
89
TX CPPI Interrupt Condition Status and Clear Registers
89
LSU Interrupt Condition Status and Clear Registers
90
Interrupt Conditions Shown in LSU_ICSR and Cleared with LSU_ICCR
90
Error, Reset, and Special Event Interrupt Condition Status and Clear Registers
91
Interrupt Clearing Sequence for Special Event Interrupts
92
Interrupt Condition Routing Registers
93
Interrupt Condition Routing Options
93
Doorbell 0 Interrupt Condition Routing Registers
94
RX CPPI Interrupt Condition Routing Registers
94
TX CPPI Interrupt Condition Routing Registers
95
LSU Interrupt Condition Routing Registers
96
Interrupt Status Decode Registers
97
Error, Reset, and Special Event Interrupt Condition Routing Registers
97
Interrupt Sources Assigned to ISDR Bits
98
Interrupt Generation
99
Interrupt Pacing
99
Example Diagram of Interrupt Status Decode Register Mapping
99
Interrupt Handling
100
Intdstn_Rate_Cntl Interrupt Rate Control Register
100
SRIO Registers
102
Introduction
102
Serial Rapidio (SRIO) Registers
102
Peripheral Identification Register (PID)
111
Peripheral ID Register (PID) - Address Offset 0000H
111
Peripheral ID Register (PID) Field Descriptions
111
Peripheral Control Register (PCR)
112
Peripheral Control Register (PCR) - Address Offset 0004H
112
Peripheral Settings Control Register (PER_SET_CNTL)
113
Peripheral Settings Control Register (PER_SET_CNTL) (Address Offset 0020H)
113
Peripheral Settings Control Register (PER_SET_CNTL) Field Descriptions
113
Peripheral Global Enable Register (GBL_EN)
116
Peripheral Global Enable Register (GBL_EN) (Address Offset 0030H)
116
Peripheral Global Enable Register (GBL_EN) Field Descriptions
116
Peripheral Global Enable Status Register (GBL_EN_STAT)
117
Peripheral Global Enable Status Register (GBL_EN_STAT) - Address 0034H
117
Peripheral Global Enable Status Register (GBL_EN_STAT) Field Descriptions
117
Block N Enable Register (Blkn_En)
119
Block N Enable Registers and the Associated Blocks
119
Block N Enable Register (Blkn_En) Field Descriptions
119
Block N Enable Status Register (Blkn_En_Stat)
120
Block N Enable Status Registers and the Associated Blocks
120
Block N Enable Status Register (Blkn_En_Stat) Field Descriptions
120
Rapidio DEVICEID1 Register (DEVICEID_REG1)
121
Rapidio DEVICEID1 Register (DEVICEID_REG1) (Offset 0080H)
121
Rapidio DEVICEID1 Register (DEVICEID_REG1) Field Descriptions
121
Rapidio DEVICEID2 Register (DEVICEID_REG2)
122
Rapidio DEVICEID2 Register (DEVICEID_REG2) (Offset 0X0084)
122
Rapidio DEVICEID2 Register (DEVICEID_REG2) Field Descriptions
122
Packet Forwarding Register N for 16-Bit Device Ids (Pf_16B_Cntln)
123
PF_16B_CNTL Registers
123
Packet Forwarding Register N for 16-Bit Deviceids (Pf_16B_Cntln) Field Descriptions
123
Packet Forwarding Register N for 8-Bit Device Ids (Pf_8B_Cntln)
124
PF_8B_CNTL Registers
124
Packet Forwarding Register N for 8-Bit Deviceids (Pf_8B_Cntln) Field Descriptions
124
SERDES Receive Channel Configuration Register N (Serdes_Cfgrxn_Cntl)
125
Serdes_Cfgrxn_Cntl Registers and the Associated Ports
125
Descriptions
125
SERDES Transmit Channel Configuration Register N (Serdes_Cfgtxn_Cntl)
128
Serdes_Cfgtxn_Cntl Registers and the Associated Ports
128
DE Bits of Serdes_Cfgtxn_Cntl
129
SWING Bits of Serdes_Cfgtxn_Cntl
129
SERDES Macro Configuration Register N (Serdes_Cfgn_Cntl)
130
Serdes_Cfgn_Cntl Registers and the Associated Ports
130
SERDES Macro Configuration Register N (Serdes_Cfgn_Cntl) Field Descriptions
130
Doorbelln Interrupt Condition Status Register (Doorbelln_Icsr)
132
Doorbelln_Icsr Registers
132
Doorbelln Interrupt Condition Status Register (Doorbelln_Icsr) Field Descriptions
132
Doorbelln Interrupt Condition Clear Register (Doorbelln_Iccr)
133
Doorbelln_Iccr Registers
133
Doorbelln Interrupt Condition Clear Register (Doorbelln_Iccr) Field Descriptions
133
RX CPPI Interrupt Status Register (RX_CPPI_ICSR)
134
RX CPPI Interrupt Condition Status Register (RX_CPPI_ICSR) - Address Offset 0240H
134
RX CPPI Interrupt Condition Status Register (RX_CPPI_ICSR) Field Descriptions
134
RX CPPI Interrupt Clear Register (RX_CPPI_ICCR)
135
RX CPPI Interrupt Condition Clear Register (RX_CPPI_ICCR) - Address Offset 0248H
135
RX CPPI Interrupt Condition Clear Register (RX_CPPI_ICCR) Field Descriptions
135
TX CPPI Interrupt Status Register (TX_CPPI_ICSR)
136
TX CPPI Interrupt Condition Status Register (TX_CPPI_ICSR) - Address Offset 0250H
136
TX CPPI Interrupt Condition Status Register (TX_CPPI_ICSR) Field Descriptions
136
TX CPPI Interrupt Clear Register (TX_CPPI_ICCR)
137
TX CPPI Interrupt Condition Clear Register (TX_CPPI_ICCR) - Address Offset 0258H
137
TX CPPI Interrupt Condition Clear Register (TX_CPPI_ICCR) Field Descriptions
137
LSU Interrupt Condition Status Register (LSU_ICSR)
138
LSU Interrupt Condition Status Register (LSU_ICSR) - Address Offset 0260H
138
LSU Interrupt Condition Status Register (LSU_ICSR) Field Descriptions
138
LSU Interrupt Condition Clear Register (LSU_ICCR)
141
LSU Interrupt Condition Clear Register (LSU_ICCR) - Address Offset 0268H
141
LSU Interrupt Condition Clear Register (LSU_ICCR) Field Descriptions
141
5.24 Error, Reset, and Special Event Interrupt Condition Status Register
142
(Err_Rst_Evnt_Icsr)
142
Error, Reset, and Special Event Interrupt Condition Status Register (ERR_RST_EVNT_ICSR) - Address Offset 0270H
142
Error, Reset, and Special Event Interrupt Condition Status Register (ERR_RST_EVNT_ICSR) Field
142
5.25 Error, Reset, and Special Event Interrupt Condition Clear Register
143
(Err_Rst_Evnt_Iccr)
143
Error, Reset, and Special Event Interrupt Condition Clear Register (ERR_RST_EVNT_ICCR) - Address Offset 0278H
143
Error, Reset, and Special Event Interrupt Condition Clear Register (ERR_RST_EVNT_ICCR) Field
143
Doorbelln_Icrr2)
144
Doorbell N Interrupt Condition Routing Registers
144
Doorbelln_Icrr Registers
144
Doorbelln Interrupt Condition Routing Register Field Descriptions
144
RX CPPI Interrupt Condition Routing Registers (RX_CPPI_ICRR and RX_CPPI_ICRR2)
145
RX CPPI Interrupt Condition Routing Registers
145
RX CPPI Interrupt Condition Routing Register Field Descriptions
145
TX CPPI Interrupt Condition Routing Registers (TX_CPPI_ICRR and TX_CPPI_ICRR2)
146
TX CPPI Interrupt Condition Routing Registers
146
TX CPPI Interrupt Condition Routing Register Field Descriptions
146
LSU Interrupt Condition Routing Registers (LSU_ICRR0-LSU_ICRR3)
147
LSU Interrupt Condition Routing Registers
147
LSU Interrupt Condition Routing Register Field Descriptions
148
Error, Reset, and Special Event Interrupt Condition Routing Registers (ERR_RST_EVNT_ICRR, ERR_RST_EVNT_ICRR2, and ERR_RST_EVNT_ICRR3)
149
Error, Reset, and Special Event Interrupt Condition Routing Registers
149
Error, Reset, and Special Event Interrupt Condition Routing Register Field Descriptions
149
Interrupt Status Decode Register (Intdstn_Decode)
150
Intdstn_Decode Registers and the Associated Interrupt Destinations
150
Interrupt Status Decode Register (Intdstn_Decode) Field Descriptions
150
Interrupt Status Decode Register (Intdstn_Decode)
151
Interrupt Status Decode Register (Intdstn_Decode)
152
Intdstn Interrupt Rate Control Register (Intdstn_Rate_Cntl)
154
Intdstn_Rate_Cntl Registers and the Associated Interrupt Destinations
154
Intdstn Interrupt Rate Control Register (Intdstn_Rate_Cntl) Field Descriptions
154
Lsun Control Register 0 (Lsun_Reg0)
155
Lsun_Reg0 Registers and the Associated Lsus
155
Lsun Control Register 0 (Lsun_Reg0) Field Descriptions
155
Lsun Control Register 1 (Lsun_Reg1)
156
Lsun_Reg1 Registers and the Associated Lsus
156
Lsun Control Register 1 (Lsun_Reg1) Field Descriptions
156
Lsun Control Register 2 (Lsun_Reg2)
157
Lsun_Reg2 Registers and the Associated Lsus
157
Lsun Control Register 2 (Lsun_Reg2) Field Descriptions
157
Lsun Control Register 3 (Lsun_Reg3)
158
Lsun_Reg3 Registers and the Associated Lsus
158
Lsun Control Register 3 (Lsun_Reg3) Field Descriptions
158
Lsun Control Register 4 (Lsun_Reg4)
159
Lsun_Reg4 Registers and the Associated Lsus
159
Lsun Control Register 4 (Lsun_Reg4) Field Descriptions
159
Lsun Control Register 5 (Lsun_Reg5)
160
Lsun_Reg5 Registers and the Associated Lsus
160
Lsun Control Register 5 (Lsun_Reg5) Field Descriptions
160
Lsun Control Register 6 (Lsun_Reg6)
161
Lsun_Reg6 Registers and the Associated Lsus
161
Lsun Control Register 6 (Lsun_Reg6) Field Descriptions
161
Lsun Congestion Control Flow Mask Register (Lsun_Flow_Masks)
162
Lsun FLOW_MASK Fields
162
Lsun_Flow_Masks Registers and the Associated Lsus
162
Lsun Congestion Control Flow Mask Register (Lsun_Flow_Masks) Field Descriptions
162
Lsun FLOW_MASK Fields
163
Queue N Transmit DMA Head Descriptor Pointer Register (Queuen_Txdma_Hdp)
164
Queuen_Txdma_Hdp Registers
164
Queue N Transmit DMA Completion Pointer Register (Queuen_Txdma_Cp)
165
Queuen_Txdma_Cp Registers
165
Queue N Receive DMA Head Descriptor Pointer Register (Queuen_Rxdma_Hdp)
166
Queuen_Rxdma_Hdp Registers
166
Queue N Receive DMA Completion Pointer Register (Queuen_Rxdma_Cp)
167
Queuen_Rxdma_Cp Registers
167
Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN)
168
Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) - Address Offset 0700H
168
Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) Field Descriptions
168
Transmit CPPI Supported Flow Mask Registers (TX_CPPI_FLOW_MASKS[0-7])
169
TX_CPPI_FLOW_MASKS Registers and the Associated TX Queues
169
Transmit CPPI Supported Flow Mask Registers
170
TX Queue N FLOW_MASK Fields
170
TX Queue N FLOW_MASK Field Descriptions
170
Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN)
172
Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) (Address Offset 0740H)
172
Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) Field Descriptions
172
Receive CPPI Control Register (RX_CPPI_CNTL)
173
Receive CPPI Control Register (RX_CPPI_CNTL) (Address Offset 0744H)
173
Receive CPPI Control Register (RX_CPPI_CNTL) Field Descriptions
173
Transmit CPPI Weighted Round Robin Control Registers (TX_QUEUE_CNTL[0-3])
174
Transmit CPPI Weighted Round Robin Control Registers
174
Transmit CPPI Weighted Round Robin Control Register Field Descriptions
175
Mailbox to Queue Mapping Registers (Rxu_Map_Ln and Rxu_Map_Hn)
177
Mailbox to Queue Mapping Registers and the Associated RX Mappers
177
Mailbox to Queue Mapping Register Pair
179
Mailbox-To-Queue Mapping Register Ln (Rxu_Map_Ln) Field Descriptions
179
Mailbox-To-Queue Mapping Register Hn (Rxu_Map_Hn) Field Descriptions
179
Flow Control Table Entry Register N (Flow_Cntln)
181
Flow_Cntln Registers
181
Flow Control Table Entry Register N (Flow_Cntln) Field Descriptions
181
Device Identity CAR (DEV_ID)
182
Device Identity CAR (DEV_ID) - Address Offset 1000H
182
Device Identity CAR (DEV_ID) Field Descriptions
182
Device Information CAR (DEV_INFO)
183
Device Information CAR (DEV_INFO) - Address Offset 1004H
183
Device Information CAR (DEV_INFO) Field Descriptions
183
Assembly Identity CAR (ASBLY_ID)
184
Assembly Identity CAR (ASBLY_ID) - Address Offset 1008H
184
Assembly Identity CAR (ASBLY_ID) Field Descriptions
184
Assembly Information CAR (ASBLY_INFO)
185
Assembly Information CAR (ASBLY_INFO) - Address Offset 100Ch
185
Assembly Information CAR (ASBLY_INFO) Field Descriptions
185
Processing Element Features CAR (PE_FEAT)
186
Processing Element Features CAR (PE_FEAT) - Address Offset 1010H
186
Processing Element Features CAR (PE_FEAT) Field Descriptions
186
Source Operations CAR (SRC_OP)
188
Source Operations CAR (SRC_OP) - Address Offset 1018H
188
Source Operations CAR (SRC_OP) Field Descriptions
188
Destination Operations CAR (DEST_OP)
189
Destination Operations CAR (DEST_OP) - Address Offset 101Ch
189
Destination Operations CAR (DEST_OP) Field Descriptions
189
Processing Element Logical Layer Control CSR (PE_LL_CTL)
190
Processing Element Logical Layer Control CSR (PE_LL_CTL) - Address Offset 104Ch
190
Processing Element Logical Layer Control CSR (PE_LL_CTL) Field Descriptions
190
Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR)
191
Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) - Address Offset 1058H
191
Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) Field Descriptions
191
Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR)
192
Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) - Address Offset 105Ch
192
Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) Field Descriptions
192
Base Device ID CSR (BASE_ID)
193
Base Device ID CSR (BASE_ID) - Address Offset 1060H
193
Base Device ID CSR (BASE_ID) Field Descriptions
193
Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK)
194
Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK) - Address Offset 1068H
194
Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK) Field Descriptions
194
Component Tag CSR (COMP_TAG)
195
Component Tag CSR (COMP_TAG) - Address Offset 106Ch
195
Component Tag CSR (COMP_TAG) Field Descriptions
195
1X/4X LP Serial Port Maintenance Block Header Register (SP_MB_HEAD)
196
1X/4X Lp_Serial Port Maintenance Block Header Register (SP_MB_HEAD) - Address Offset 1100H
196
Port Link Time-Out Control CSR (SP_LT_CTL)
197
Port Link Time-Out Control CSR (SP_LT_CTL) - Address Offset 1120H
197
Port Link Timeout Control CSR (SP_LT_CTL) Field Descriptions
197
Port Response Time-Out Control CSR (SP_RT_CTL)
198
Port Response Time-Out Control CSR (SP_RT_CTL) - Address Offset 1124H
198
Port Response Time-Out Control CSR (SP_RT_CTL) Field Descriptions
198
Port General Control CSR (SP_GEN_CTL)
199
Port General Control CSR (SP_GEN_CTL) - Address Offset 113Ch
199
Port General Control CSR (SP_GEN_CTL) Field Descriptions
199
Port Link Maintenance Request CSR N (Spn_Lm_Req)
200
Spn_Lm_Req Registers and the Associated Ports
200
Port Link Maintenance Request CSR N (Spn_Lm_Req) Field Descriptions
200
Port Link Maintenance Response CSR N (Spn_Lm_Resp)
201
Spn_Lm_Resp Registers and the Associated Ports
201
Port Link Maintenance Response CSR N (Spn_Lm_Resp) Field Descriptions
201
Port Local Ackid Status CSR N (Spn_Ackid_Stat)
202
Spn_Ackid_Stat Registers and the Associated Ports
202
Port Local Ackid Status CSR N (Spn_Ackid_Stat) Field Descriptions
202
Port Error and Status CSR N (Spn_Err_Stat)
203
Spn_Err_Stat Registers and the Associated Ports
203
Port Error and Status CSR N (Spn_Err_Stat) Field Descriptions
203
Port Control CSR N (Spn_Ctl)
206
Spn_Ctl Registers and the Associated Ports
206
Port Control CSR N (Spn_Ctl) Field Descriptions
206
Error Reporting Block Header Register (ERR_RPT_BH) - Address Offset 2000H
209
Error Reporting Block Header Register (ERR_RPT_BH) Field Descriptions
209
Logical/Transport Layer Error Detect CSR (ERR_DET) - Address Offset 2008H
210
Logical/Transport Layer Error Enable CSR (ERR_EN) - Address Offset 200Ch
212
Logical/Transport Layer Error Enable CSR (ERR_EN) Field Descriptions
212
Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT) - Address Offset 2010H
214
Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT) Field Descriptions
214
Logical/Transport Layer Address Capture CSR (ADDR_CAPT) - Address Offset 2014H
215
Logical/Transport Layer Address Capture CSR (ADDR_CAPT) Field Descriptions
215
Logical/Transport Layer Device ID Capture CSR (ID_CAPT) - Address Offset 2018H
216
Logical/Transport Layer Device ID Capture CSR (ID_CAPT) Field Descriptions
216
Logical/Transport Layer Control Capture CSR (CTRL_CAPT) - Address Offset 201Ch
217
Logical/Transport Layer Control Capture CSR (CTRL_CAPT) Field Descriptions
217
Port-Write Target Device ID CSR (PW_TGT_ID) - Address Offset 2028H
218
Port-Write Target Device ID CSR (PW_TGT_ID) Field Descriptions
218
Port Error Detect CSR N (Spn_Err_Det)
219
Spn_Err_Det Registers and the Associated Ports
219
Port Error Detect CSR N (Spn_Err_Det) Field Descriptions
219
Port Error Rate Enable CSR N (Spn_Rate_En)
221
Spn_Rate_En Registers and the Associated Ports
221
Port Error Rate Enable CSR N (Spn_Rate_En) Field Descriptions
221
Port N Attributes Error Capture CSR 0 (Spn_Err_Attr_Capt_Dbg0)
223
Spn_Err_Attr_Capt_Dbg0 Registers and the Associated Ports
223
Port N Error Capture CSR 1 (Spn_Err_Capt_Dbg1)
224
Spn_Err_Capt_Dbg1 Registers and the Associated Ports
224
Port N Error Capture CSR 1 (Spn_Err_Capt_Dbg1) Field Descriptions
224
Port N Error Capture CSR 2 (Spn_Err_Capt_Dbg2)
225
Spn_Err_Capt_Dbg2 Registers and the Associated Ports
225
Port N Error Capture CSR 2 (Spn_Err_Capt_Dbg2) Field Descriptions
225
Port N Error Capture CSR 3 (Spn_Err_Capt_Dbg3)
226
Spn_Err_Capt_Dbg3 Registers and the Associated Ports
226
Port N Error Capture CSR 3 (Spn_Err_Capt_Dbg3) Field Descriptions
226
Port N Error Capture CSR 4 (Spn_Err_Capt_Dbg4)
227
Spn_Err_Capt_Dbg4 Registers and the Associated Ports
227
Port N Error Capture CSR 4 (Spn_Err_Capt_Dbg4) Field Descriptions
227
Port Error Rate CSR N (Spn_Err_Rate)
228
Spn_Err_Rate Registers and the Associated Ports
228
Port Error Rate CSR N (Spn_Err_Rate) Field Descriptions
228
Port Error Rate Threshold CSR N (Spn_Err_Thresh)
229
Spn_Err_Thresh Registers and the Associated Ports
229
Port Error Rate Threshold CSR N (Spn_Err_Thresh) Field Descriptions
229
Port IP Discovery Timer for 4X Mode Register (SP_IP_DISCOVERY_TIMER) - Address Offset 12000H
230
Port IP Mode CSR (SP_IP_MODE) - Address Offset 12004H
231
Port IP Mode CSR (SP_IP_MODE) Field Descriptions
231
Port IP Prescaler Register (IP_PRESCAL) - Address Offset 12008H
233
Port IP Prescaler Register (IP_PRESCAL) Field Descriptions
233
Port-Write-In Capture Csrs
234
Port-Write-In Capture CSR Field Descriptions
234
Spn_Rst_Opt Registers and the Associated Ports
235
Port Reset Option CSR N (Spn_Rst_Opt) Field Descriptions
235
Spn_Ctl_Indep Registers and the Associated Ports
236
Port Control Independent Register N (Spn_Ctl_Indep) Field Descriptions
236
Spn_Silence_Timer Registers and the Associated Ports
238
Port Silence Timer N Register (Spn_Silence_Timer) Field Descriptions
238
Port Multicast-Event Control Symbol Request Register N (Spn_Mult_Evnt_Cs)
239
Spn_Mult_Evnt_Cs Registers and the Associated Ports
239
Spn_Cs_Tx Registers and the Associated Ports
240
Port Control Symbol Transmit N Register (Spn_Cs_Tx) Field Descriptions
240
Index
241
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Texas Instruments TMS320TCI648x User Manual (33 pages)
DSP 64-Bit Timer
Brand:
Texas Instruments
| Category:
Timer
| Size: 0.25 MB
Table of Contents
Table of Contents
3
Preface
5
Introduction to the Timer
6
Timer Block Diagram
7
Generation of the Internal Timer Clock
7
Timer Modes
8
64-Bit Timer Mode
8
Dual 32-Bit Timer Modes
8
64-Bit Timer Mode Block Diagram
8
Dual 32-Bit Timers Chained Mode Block Diagram
9
Dual 32-Bit Timers Chained Mode Example
10
Dual 32-Bit Timers Unchained Mode Block Diagram
10
Dual 32-Bit Timers Unchained Mode Example
11
Counter and Period Registers Used in GP Timer Modes
12
Timer Operation
13
Timer Mode Selection
13
Timer Enabling
13
Timer Clock Source Selection
14
Timer Output Mode Selection
14
Timer Clock Source Block Diagram
14
Timer Counting
15
Timer Reset Sources
15
Timer Interrupt Rate
15
Timer Emulation Modes
16
Timer Operation Boundary Conditions
16
Timer Emulation Modes Selection
16
Timer Operation When Timer Count = 0 and Timer Period
16
32-Bit Timer Counter Overflow Example
17
Reading Counter Registers
17
3.10 Initializing the Timer
18
Timer Initialization
18
Watchdog Timer Mode
19
Timer Output Signal and Timer Interrupt Signal in Watchdog Mode
19
Watchdog Timer Mode Restrictions
19
Watchdog Timer Mode Operation
19
Timer in Watchdog Timer Mode
20
Watchdog Timer Operation State Diagram
21
Watchdog Timer Register Write Protection
22
Timer Registers
23
Emulation Management and Clock Speed Register (EMUMGT_CLKSPD)
24
Emulation Management and Clock Speed Register (EMUMGT_CLKSPD) Field Descriptions
24
Timer Counter Registers (CNTHI and CNTLO)
25
64-Bit Timer Counter Register
25
Timer Counter Registers (CNTHI and CNTLO) Field Descriptions
25
Timer Period Registers (PRDHI and PRDLO)
26
64-Bit Timer Period Register
26
Timer Period Registers (PRDHI and PRDLO) Field Descriptions
26
Timer Control Register (TCR)
27
Timer Control Register (TCR) Field Descriptions
27
Timer Global Control Register (TGCR)
30
Timer Global Control Register (TGCR) Field Descriptions
30
Watchdog Timer Control Register (WDTCR)
31
Watchdog Timer Control Register (WDTCR) Field Descriptions
31
Appendix A Revision History
32
Tci648X/C6472 Timer Revision History
32
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