Differential Serdes; Power Management-Using Suspend/Awake; I/O Standards And I/O Banking Rules; Simultaneous Switching Output (Sso) Management - Xilinx Spartan-6 FPGA Series Design And Pin Planning Manual

Differential SerDes

Differential I/O can be serialized up to 8:1 with each P/N differential pair.
Power Management—Using Suspend/Awake
When using the Suspend function, the functionality of the AWAKE pin is also required.
Consequently, the AWAKE pin can not be used as user I/O. When using the multi-pin
wakeup option, the SCP[0:7] pins become multi-function pins.
A complete description of Suspend/Awake is outlined in UG394, Spartan-6 FPGA Power
Management User Guide.

I/O Standards and I/O Banking Rules

The I/O standards and other I/O attributes must be defined for each I/O pin in the design.
Chapter 1 of the Spartan-6 FPGA SelectIO Resources User Guide describes all of the I/O
banking rules associated with the available standards and attributes, particularly the
section on I/O Standard Bank Compatibility. For example, for many differential standards,
the outputs are only available in banks 0 and 2. To check I/O standard compatibility and
for any I/O banking restrictions, run the DRCs in the PlanAhead tool.

Simultaneous Switching Output (SSO) Management

Proposed pin placements must be checked against the SSO limits table in the Spartan-6
FPGA Data Sheet: DC and Switching Characteristics. If violations are determined, first try to
spread the offending outputs into other I/O banks (if possible).
Read the Simultaneous Switching Outputs section of the Spartan-6 FPGA SelectIO Resources
User Guide for a more detailed discussion on SSOs, and for specific recommendations for
pin-planning to avoid issues related to SSOs.

Running Design Rule Checks

The DRCs, available in the software tools, are used to validate clocking and pin
assignments. Basic DRCs can be run with as little as a pin-list with defined I/O standards.
Full DRCs for pin placement validation are run when compiling the design in the ISE
software. The more complete the I/O and clocking structures are in the design, the more
complete the DRCs. To completely validate pin placements, ensure that all I/O interfaces
and clocking structures have been entered into the design.
I/O banking rule DRCs can be accessed in the PlanAhead tool with as little as a pin-list and
defined I/O standards and attributes. Clock topology and resource DRCs are available by
running the design through the ISE software.
Confirm in the clocking and I/O DRCs that all Intellectual Property with unique clocking
requirements have been entered into the design.
In designs that require regional clocks in addition to global clocks, ensure that each
regional clock is entered in the design and has at least a few representative loads attached.
Any I/O clocks with regional requirements should have all loads defined.
In addition to pin planning to avoid DRC violations, planning the pinout to optimize
performance of a particular design is also important as well as considering the overall flow
Spartan-6 FPGA PCB Design and Pin Planning
UG393 (v1.1) April 29, 2010
Power Management—Using Suspend/Awake
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