Xilinx Spartan-6 FPGA Series Design And Pin Planning Manual page 55

X-Ref Target - Figure 5-14
As a general rule, the P and N paths need to be kept at equal lengths through a transition.
Where possible, via stub length should be kept to a minimum by traversing the signal
through the entire length of the vias. The analysis shown in
S-parameter return loss for common-mode (SCC11) and differential (SDD11) responses.
X-Ref Target - Figure 5-15
From the graph in
return loss. The much worse common-mode response relative to the differential response
is the reason why it is a good idea to reduce P/N skew as much as possible before entering
a transition. The 60/40 rule of thumb is 40 dB of return loss at 1 GHz, which implies 60 fF
of excess capacitance. Because excess capacitance is a single pole response, simple
extrapolation rules can be used. For example, a shift to 34 dB return loss doubles the excess
capacitance. Due to the excellent performance characteristics of GSSG vias, even long via
stubs only double the differential via's capacitance at the most.
Spartan-6 FPGA PCB Design and Pin Planning
UG393 (v1.1) April 29, 2010
From Pin L11, Exiting at Lower Layer
Figure 5-14: Differential GSSG Via in 16-Layer PCB from Pins L11 and L6
0
-20
-40
-60
-80
1E8
Figure 5-15: Simulated Return Loss Comparing Differential and Common-Mode
Losses for L11 and L6 GSSG Vias
Figure 5-15, the common-mode response is 20 dB worse in terms of
www.xilinx.com
From Pin L6, Exiting at Middle Layer
Figure 5-15
1E9
Frequency, Hz
UG393_c5_15_091809
Differential Vias
UG393_c5_14_091809
compares the
1E10
55