Xilinx Spartan-6 FPGA Series Design And Pin Planning Manual page 48

Chapter 5: Design of Transitions for High-Speed Signals
X-Ref Target - Figure 5-1
X-Ref Target - Figure 5-2
The magnitude of this excess capacitance (C) or inductance (L) can also be extracted from
the TDR waveform by integrating the normalized area of the transition's TDR response.
The respective equations for capacitance and inductance are:
Figure 5-3
X-Ref Target - Figure 5-3
48
Td
2Td
Figure 5-1: TDR Signature of Shunt Capacitance
Figure 5-2: TDR Signature of Series Inductance
t2
V
2
∫
------------------------------------ - dt
C
= – ----- -
Z
0
t1
t2
V
∫
------------------------------------ - dt
L 2Z
=
0
t1
shows the integration of the normalized TDR area.
t
1
Shaded area goes into the
integral for Equation 13-2
Figure 5-3: Integration of Normalized TDR Area
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C
t ( ) V
–
tdr step
V
step
t ( ) V
–
tdr step
V
step
t
2
UG393_c5_03_091809
Spartan-6 FPGA PCB Design and Pin Planning
50Ω
UG393_c5_01_091809
50Ω
UG393_c5_02_091809
Equation 5-1
Equation 5-2
UG393 (v1.1) April 29, 2010