Fpga Mounting Inductance - Xilinx Spartan-6 FPGA Series Design And Pin Planning Manual

Chapter 2: Power Distribution System
Spreading inductance acts like any other inductance and resists changes to the amount of
current in a power plane (the conductor). The inductance retards the capacitor's ability to
respond to a device's transient currents and should be reduced as much as possible.
Because the designer's control over the X-Y shape of the plane can be limited, the only
controllable factor is the spreading inductance value. This is determined by the thickness
of the dielectric separating a power plane from its associated ground plane.
For high-frequency power distribution systems, power and ground planes work in pairs,
with their inductances coexisting dependently with each other. The spacing between the
power and ground planes determines the pair's spreading inductance. The closer the
spacing (the thinner the dielectric), the lower the spreading inductance. Approximate
values of spreading inductance for different thicknesses of FR4 dielectric are shown in
Table
Table 2-3: Capacitance and Spreading Inductance Values for Different Thicknesses
of FR4 Power-Ground Plane Sandwiches
Decreased spreading inductance corresponds to closer spacing of V
When possible, place the V
stackup. Facing V
use of V
(lead frames, wire bond packages), the speeds involved and the sheer amount of power
required for fast, dense devices often demand it.
Besides offering a low-inductance current path, power-ground sandwiches also offer some
high-frequency decoupling capacitance. As the plane area increases and as the separation
between power and ground planes decreases, the value of this capacitance increases.
Capacitance per square inch is shown in

FPGA Mounting Inductance

The PCB solder lands and vias that connect the FPGA power pins (V
contribute an amount of parasitic inductance to the overall power circuit. For existing PCB
technology, the solder land geometry and the dogbone geometry are mostly fixed, and
parasitic inductance of these geometries does not vary. Via parasitic inductance is a
function of the via length and the proximity of the opposing current paths to one another.
The relevant via length is the portion of the via that carries transient current between the
FPGA solder land and the associated V
power plane and the PCB backside) does not affect the parasitic inductance of the via (the
shorter the via between the solder lands and the power plane, the smaller the parasitic
inductance). Parasitic via inductance in the FPGA mounting is reduced by keeping the
relevant V
stackup).
Device pinout arrangement determines the proximity of opposing current paths to one
another. Inductance is associated with any two opposing currents (for example, current
flowing in a V
26
2-3.
Dielectric Thickness
(micron) (mil)
102 4
51 2
25 1
CC
and GND planes are sometimes referred to as sandwiches. While the
CC
– GND sandwiches was not necessary in the past for previous technologies
CC
and GND planes as close to the FPGA as possible (close to the top of the PCB
CC
and GND via pair). A high degree of mutual inductive coupling between
CC
www.xilinx.com
Inductance
(pH/square)
130
65
32
planes directly adjacent to the GND planes in the PCB
Table 2-3.
or GND plane. Any remaining via (between the
CC
Spartan-6 FPGA PCB Design and Pin Planning
Capacitance
2 2
(pF/in ) (pF/cm )
225 35
450 70
900 140
and GND planes.
CC
and GND)
CC
UG393 (v1.1) April 29, 2010