0402 Ceramic Capacitor - Xilinx Spartan-6 FPGA Series Design And Pin Planning Manual

0402 Ceramic Capacitor

The 0.47 µF 0402 capacitor covers the high-middle frequency range. Placement and
mounting are critical for these capacitors.
The capacitor should be mounted as close to the FPGA as possible (achieves the least
parasitic inductance possible).
For PCBs with a total thickness of < 1.575 mm (62 mils), the best placement location is on
the PCB backside, within the device footprint (in the empty cross with an absence of vias).
V
array. Where space is available, 0402 mounting pads should be added and connected to
these vias.
For PCBs with a total thickness > 1.575 mm (62 mils), the best placement location could be
on the PCB top surface. The depth of the V
factor: if the V
surface is optimal; if the V
placement on the bottom PCB surface is optimal.
Any 0402 capacitors placed outside the device footprint (whether on the top or bottom
surface) should be within 0.5 inch of the device's outer edge.
The capacitor mounting (solder lands, traces, and vias) must be optimized for low
inductance. Vias should be butted against the pads with no trace length in-between. These
vias should be at the sides of the pads if at all possible (see
the sides of the pads decreases the mounting's parasitic inductance by increasing the
mutual inductive coupling of one via to the other. Dual vias can be placed on both sides of
the pads (see
returns.
Many manufacturing rules prevent mounting any device within 0.1 inch of the FPGA on
the PCB top surface. Manufacturing rules can also prevent capacitor placement on the PCB
backside within the device footprint, whether because backside mounting is prohibited or
geometries necessary to fit mounting pads in the tight spaces between vias are too small
for reliable soldering. These rules decrease the available options for capacitor placement
but do not preclude meeting the Xilinx placement recommendations. Discuss any specific
concerns with a PCB fabrication, assembly, and/or quality department.
Spartan-6 FPGA PCB Design and Pin Planning
UG393 (v1.1) April 29, 2010
and GND vias corresponding to the supply of interest should be identified in the via
CC
plane is in the PCB stackup's top half, capacitor placement on the top PCB
CC
CC
Figure 2-2D) for even lower parasitic inductance, but with diminishing
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plane of interest in the PCB stackup is the key
CC
plane is in the PCB stackup's bottom half, capacitor
PCB Decoupling Capacitors
Figure 2-2C). Via placement at
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