Pds Measurements; Noise Magnitude Measurement - Xilinx Spartan-6 FPGA Series Design And Pin Planning Manual

PDS Measurements

Measurements can be used to determine whether a PDS is adequate. PDS noise
measurements are a unique task, and many specialized techniques have been developed.
This section describes the noise magnitude and noise spectrum measurements.

Noise Magnitude Measurement

Noise measurement must be performed with a high-bandwidth oscilloscope (minimum
3 GHz oscilloscope and 1.5 GHz probe or direct coaxial connection) on a design running
realistic test patterns. The measurement is taken at the device's power pins or at an unused
I/O driven High or Low (referred to as a spyhole measurement).
V
measured this way, but more accurate results are obtained by measuring static (fixed logic
level) signals at unused I/Os in the bank of interest.
When making the noise measurement on the PCB backside, the via parasitics in the path
between the measuring point and FPGA must be considered. Any voltage drop occurring
in this path is generally in opposition to the noise, and therefore is not accounted for in the
oscilloscope measurement.
PCB backside via measurements also have a potential problem: decoupling capacitors are
often mounted directly underneath the device, meaning the capacitor lands connect
directly to the V
measurement by acting like a short circuit for the high-frequency AC current. To make sure
the measurements are not shorted by the capacitors, remove the capacitor at the
measurement site (keep all others to reflect the real system behavior).
When measuring V
driver to logic 1 or logic 0. In most cases, the same I/O standard should be used for this
"spyhole" as for the other signals in the bank. Measuring a static logic 0 shows the
crosstalk (via field, PCB routing, package routing) induced on the victim. Measuring a
static logic 1 shows all the same crosstalk components as well as the noise present on the
V
logic 0 from the noise measured on static logic 1, the noise on V
viewed. For an accurate result, the static logic 0 and static logic 1 noise must be measured
at the same I/O location. This means storing the time-domain waveform information from
both logic states and performing the subtraction operation on the two waveforms in a post-
process math computation tool such as MATLAB or Excel.
Oscilloscope Measurement Methods
There are two basic ways of using the oscilloscope to view power system noise, each for a
different purpose. The first surveys all possible noise events, while the second is useful for
focusing on individual noise sources.
•
•
Power system noise measurements should be made at a few different FPGA locations to
ensure that any local noise phenomena are captured.
Spartan-6 FPGA PCB Design and Pin Planning
UG393 (v1.1) April 29, 2010
and V can only be measured at the PCB backside vias. V
CCINT CCAUX
and GND vias with surface traces. These capacitors confuse the
CC
noise, the measurement can be taken at an I/O pin configured as a
CCO
net for the I/O bank. By subtracting (coherently in time) the noise measured on static
CCO
Place the oscilloscope in infinite persistence mode to acquire all noise over a long time
period (many seconds or minutes). If the design operates in many different modes,
using different resources in different amounts, these various conditions and modes
should be in operation while the oscilloscope is acquiring the noise measurement.
Place the oscilloscope in averaging mode and trigger on a known aggressor event.
This can show the amount of noise correlated with the aggressor event (any events
asynchronous to the aggressor are removed through averaging).
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PDS Measurements
can also be
CCO
at the die can be
CCO
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