Chapter 3: Selectio Signaling; Interface Types; Single-Ended Versus Differential Interfaces - Xilinx Spartan-6 FPGA Series Design And Pin Planning Manual

SelectIO Signaling
The Spartan-6 FPGA SelectIO resources are the general-purpose I/O and its various
settings. With numerous I/O standards and hundreds of variants within these standards,
these SelectIO resources offer a flexible array of choices for designing I/O interfaces.
This chapter provides some strategies for choosing I/O standard, topography, and
termination, and offers guidance on simulation and measurement for more detailed
decision making and verification. In many cases, higher-level aspects of the system (other
device choices or standards support) define the I/O interfaces to be used. In cases where
such constraints are not defined, it is up to the system designer to choose I/O interface
standards and optimize them according to the purpose of the system.
This chapter contains the following sections:
•
•

Interface Types

To better address the specifics of the various interface types, it is necessary to first break
interfaces into categories. Two relevant divisions are made:
•
•

Single-Ended versus Differential Interfaces

Traditional digital logic uses single-ended signaling – a convention that transmits a signal
and assumes a GND common to the driver and receiver. In single-ended interfaces, a
signal's assertion (whether it is High or Low) is based on its voltage level relative to a fixed
voltage threshold that is referenced to GND. When the voltage of the signal is higher than
the V
than the V
single-ended I/O standard.
To reach higher interface speeds and increase noise margin, some single-ended I/O
standards rely on a precise dedicated local reference voltage other than GND. HSTL and
SSTL are examples of I/O standards that rely on a V
thought of as a fixed comparator input.
Higher-performance interfaces typically make use of differential signaling – a convention
that transmits two complementary signals referenced to one another. In differential
interfaces, a signal's assertion (whether it is High or Low) is based on the relative voltage
levels of the two complementary signals. When the voltage of the P signal is higher than
the voltage of the N signal, the state is considered High. When the voltage of the N signal
Spartan-6 FPGA PCB Design and Pin Planning
UG393 (v1.1) April 29, 2010
Interface Types
Single-Ended Signaling
Single-Ended versus Differential Interfaces
SDR versus DDR Interfaces
threshold, the state is considered High. When the voltage of the signal is lower
IH
threshold, the state is considered Low. TTL is one common example of a
IL
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Chapter 3
to resolve logic levels. V
REF
can be
REF
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